TRS-80 Tech. manual (was: help with TRS-80 Model II?)

From: Cord Coslor <archive_at_navix.net>
Date: Wed Aug 13 11:37:38 1997

I have a TRS-80 technical manual... any interest.

Christopher Denham wrote:

> On Sun, 11 Jan 1998 17:03:28 +0000 (GMT), you wrote:
>
> >>
> >> On Sun, 11 Jan 1998, Tony Duell wrote:
> >>
> >> ........
> >> > What is the reset pin doing at the Z80? And what is the WAIT* pin doing.
> >> > I wonder if the CPU is either stuck in the reset state, or in a wait
> >> > state.
> >>
> >> RESET* is low for about 500 ms after power-on, then goes high. WAIT* is
> >> always high.
> >>
> >> > I'm pretty sure that if the CPU is halted, it continues to produce
> >> > refresh addresses, so you'd see some activity on the address lines and on
> >> > RFSH*. Can't hurt to check, though.
> >>
> >> RFSH* is at a solid 1.4v, and doesn't move with a pull-up.
> >
> >Wait a second... It's at a constant, DC 1.4V? Are you sure?
> >
> >You're not missing a power line, are you? I suppose a low supply rail on
> >chips driven by this signal could cause some strange happenings. Check
> >all the outputs from the power supply with a 'scope. Apart from that, I
> >am confused. There's no way a TTL output should be stuck at that voltage.
> >
> >
> >> part is tri-stated. Data bus lines D0-D2 and D7 are at a firm 1.4v. D3
> >> is tri-stated and can be pulled to 5v. D4-D6 are low and pull-up to 1.4v.
> >
> >Kersqueeble... What on earth is going on here.
> >
> >> Now, here's where it gets interesting. NMI* had an irregular pulse train
> >> coming into it- at the same time the display was flickering. I shut off
> >
> >There may well be an interrupt from the display system to the CPU - a
> >sort of poor-mans heartbeat for the real time clock.
> >
> >
> >> and turned on again, and the display was blank and NMI* was high. INT*,
> >> WAIT*, BUSRQ*, and RESET* are high, BUSAK* is low, and HALT*, MREQ*,
> >> IORQ*, RD*, WR*, M1*, and RFSH* are all at a solid 1.4v. (???)
> >
> >That 1.4V worries me. What about the buffers on these signals? Are they
> >getting the 5V power?
> >
> >>
> >> > Do you have a schematic of the gate-array version of the M4 CPU board?
> >> > I've got an M4 here with said board, and it's the only part of the system
> >> > that's not covered in the M3 Techref (which I also have), so I am looking
> >> > for a copy/scanned in version of the diagram.
> >> >
> >> > I would buy a Model 4 technical manual, but Tandy in the UK are totally
> >> > clueless and assured me that there was no such machine as a 'TRS-80' :-)
> >>
> >> I have a 6-page schematic for the CPU, and it shows 4 PAL's. It is dated
> >> 23 Feb 1983. Contact me privately and we'll work out how to get it from
> >> here to there.
> >
> >Alas, I think that's the older version of the CPU board. Is there a 6845
> >on it? Later versions, like the one in my machine, have a custom Tandy 40
> >pin gate array alongside the CPU which contains most of the video
> >circuitry, etc.
> >
> >On the other hand, it's a lot better than nothing, so if you could make a
> >copy of it, we can come to some arrangement about getting it to me.
> >
> >
> >>
> >> Richard Schauer
> >> rws_at_ais.net
> >
> I have a TRS-80 MODEL II TECHNICAL REFERENCE HANDBOOK
> Catalog Number 26-4921 dated 1980 and a flatbed scanner so any pages
> you would like to see i could email them to you direct .........
>
> Cheers Chris Denham cdenham_at_tgis.co.uk



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|  Cord G. Coslor   : archive_at_navix.net   |
| Deanna S. Wynn    : deannasue_at_navix.net |
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Received on Wed Aug 13 1997 - 11:37:38 BST

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