CLASSICCMP digest 241

From: <(>
Date: Fri Nov 21 12:24:00 1997

> <Are there any obvious choices of better cores for a simple homemade
> <core plane? I might try playing with steel 0-80 (and smaller) nuts
> Permalloy was a common one and the size was generally 50 mils or smaller.
> TX2 used this with 80mil od and 50 mil ID, it switch time was 1uS and
> required 800ma to switch and yeilded 100mv if it switched. There was
> no data given if it didn't switch but I'd bet 20mv would be believable.
> Cycle time for a memory with cores like that would be 3-5us. The TX2
> ran them at 5uS.
800mA to switch! Ouch! No wonder the PSU was so bulky.

> Other materials can be used but a good sharp B-H curve is desired and
> saturable ferrites were used for the smaller 30-40 mil cores. Saturable
> ferrites are used in power conversion in current designs so they exist.
> There is a relationship between core size, material and speed.
> <this weekend, but I doubt they'll be particularly good - probably it'll
> <take a rather sizable current*turns product to magnetize these.
> Turns are 1, and the current from some of the older stuff was around
> 400-800ma and the smaller later stuff in the 100-200ma region.
> <Assuming I do find a readily available material that works, would others
> <be interested in a write-up about building your own core memory plane?
> <I'm envisioning circuitry to allow one to toggle in bits to various
> <locations and read them out again. The logic driving it is likely
> <to be simple TTL (maybe some 74LS138's or 74154's for X-Y decoders)
> <plus some analog electronics for the drivers and sense/inhibit
> <circuitry. If I'm clever enough, it'll be be doable with readily
> <available (i.e. Radio Shack) parts.
> This would be interesting. Additionally if it could be applied to some
> of the core planes out there with ??? characteristics and origins it may
> help. there was an article written back in the late 70s in BYTE on using
> CC core memories.
> FYI the TX2 used 64x64(4kbit) core planes for main memory to make a larger
> 256x256x38 bit memory. The fast memory(registers) were 64x19bits using two
> cores per bit (bigger signal less noise). the array was 8x8 using 128
> cores.
> A small 8x8 or 16x16 array would be trivial to wire and drive. It's the
> timing for the read pulse and keeing noise out of things that is twitchy.

Truth. Trying to time right time to catch the bounce back and avoid
the read pulse that is there on the sense wire. Yeah, it's read in
serially fashion because that one wire is strung back and forth
through all cores just once. You have to fashion the circuit to
retore the orignal bits because the read process destroys the data.

Good info how that core worked in general sense was shown in LIFE
computer storage. Find it if you can at local library.
> Allison

Received on Fri Nov 21 1997 - 12:24:00 GMT

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