Replies to various threads

From: Allison J Parent <>
Date: Thu Apr 23 13:33:28 1998

<> The PDP-11 architecture has only 7 GP registers (since you can't really
<> the PC for just anything) but that's good for the times, and they reall
<> are interchangable, so I'd be willing to argue that it wins on that.
<I'm glad somebody agrees with me on that! IMHO the concept of a GP
<register is a RISC sort of thing. And, Allison, if you think RISC
<should be register-rich, I claim the PDP11 was for its date, and
<certainly was compared to micros of the 1970s.

Compared to maybe 6800 or 6502, the 8080 had 4 16bit registers (bc, de,
hl, sp). The z80 added a second set and IX/IY. But that was only one

On the instructions RISC systems of the time and even later didn't have
the addressing modes and often had a distinct register load and store
instruction. The best example of that difference was an ADD (R1),_at_(r2)+.
Now compare that to the DG Nova and it is of a stark difference.

Of all the micros in my collection, none are RISC save for the PDP-8 and
6502 which in my mind come close.

I have: 1802, SC/MP, 6800, 6809, NEC D78PG11, 8748/9, 8751, 8080/8085,
z80, z180, z280, z8002, z8001, 808x, 8018x, 80286, 80386, 80486 and the
micro version of minis 6100(pdp-8), 6120(PDP-8+EMA) TI9900, PDP11(T-11,
F11, J-11).

Now something with a MIPS chip, ARM, sparc or some such would be a great
addition of a real RISC processor.

<I don't like the "one instruction per cycle" definition of RISC - for a s
<what is a cycle? I prefer to think of RISC as an "every cycle is sacred"
<philosophy - you don't waste cycles. I'd try to get _memory cycles_ as o
<as the hardware permits them - on the 6502, for example, one per cycle (a
<almost manages it!), on 8080/Z80/PDP one every two or three cycles - but
<wouldn't make them all instruction fetches!

Again the -11 fails on that definition. Typical instruction are several
clocks per cycle and several cycles per instruction. Now the Z280
approaches that at the bus level as it has a internal cache and pipline
but, the instruction set is non-risc.

<Except the early ones. Allison, are you sure it was the 11/05? I claim
<it was the 11/15 (I have an 05). However I will concede that 05 may
<have at one time been a name for an 11/20 variant.

It may have been the 15.

I'm not saying RISC is bad only that the PDP-11 is not RISC.

Received on Thu Apr 23 1998 - 13:33:28 BST

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