Replies to various threads

From: Captain Napalm <spc_at_armigeron.com>
Date: Thu Apr 23 13:29:06 1998

  Just in case anyone doesn't know, the expansions of CISC and RISC are:

        CISC - Complex Instruction Set Computer (or CPU)
        RISC - Reduced Instruction Set Computer (or CPU)

  RISC (as a separate concept) came about when it was noticed that most
compilers generally didn't use all the instructions or addressing modes that
a CPU could support, since supporting those oddball instructions and/or
addressing modes meant that the compiler had to be more complex which wasn't
always possible (due to size constraints, programmer ability, or time
constraints).

  Typical compilers tended to use the simpler instructions (MOV/LD/ST being
the most commonly used ones, followed by the ALU ops) and either reg-reg or
reg-memory (if applicable) addressing modes. It was felt that making the
instruction set compiler friendly (simple instructions, simple addressing
modes) and concentrating on making it fast would more than make up for the
loss of the more esoteric opcodes and addressing modes.

  The first commercially availble RISC system (from IBM no less!) had
variable length instructions, but they were simple and fast (well, fast for
the time and for IBM). Other research lead to making the instructions the
same size, thus the execution of an instruction could be deterministically
known and making pipelining easier to do (I wonder how much Intel has spent
on pipelining the 80x86 line). Since the number of addressing modes was
limited, but since the CPU itself was simpler and smaller than a comparible
CISC one, more space could be set aside for registers, again to make up
speed.

  It really comes down do shoving the complexity elsewhere. Today's RISC
chips are very complex in terms of caching, pipelining, multiple execution
units, branch predictions, delay slots and what not and the pendulum is
slowing coming back around to CISC like ideas, now that we understand
compiler technology better and have better tools to construct such beasts.

It was thus said that the Great Philip.Belben_at_powertech.co.uk once stated:
> Pete Turnbull:
>
> > The PDP-11 architecture has only 7 GP registers (since you can't really use
> > the PC for just anything) but that's good for the times, and they really
> > are interchangable, so I'd be willing to argue that it wins on that.
>
> I'm glad somebody agrees with me on that! IMHO the concept of a GP
> register is a RISC sort of thing. And, Allison, if you think RISC
> should be register-rich, I claim the PDP11 was for its date, and
> certainly was compared to micros of the 1970s.

  And given the right definition of RISC, even the 6502 could qualify.

> I don't like the "one instruction per cycle" definition of RISC - for a start,
> what is a cycle? I prefer to think of RISC as an "every cycle is sacred"
> philosophy - you don't waste cycles. I'd try to get _memory cycles_ as often
> as the hardware permits them - on the 6502, for example, one per cycle (and it
> almost manages it!), on 8080/Z80/PDP one every two or three cycles - but I
> wouldn't make them all instruction fetches!

  Using that definition, I think even the VAX might qualify.

  Actually, while the VAX is usually considered the CISCish of the CISC
machines, in a sense it's very RISCish too---all instructions are very
regular and support all the addressing modes, it has a slew of general
purpose registers and for the time, was fairly compiler friendly. Perhaps
if DEC had spent the money improving the VAX that Intel did for the 80x86 we
might have the Pentium killer 8-)

  -spc (What goes around comes around)
Received on Thu Apr 23 1998 - 13:29:06 BST