OT, but info needed: RAM uprade

From: Allison J Parent <allisonp_at_world.std.com>
Date: Wed Dec 30 17:48:28 1998

<If I understood, this could be summed up as:
<When an interrupt happens, the interrupt line is pulled low by the
<interrupting device. If it's edge triggered, the CPU can't tell how many
<devices are causing the interrupt and only services the first one.

Assuming the interrupt was active low. the PC made it worse by being edge
and active high...poor.

<And are you saying that if they were level-triggered, I could have two
<devices on IRQ 7?


<And is it easy to design a level-triggered equivalent
<to the PC on paper?

Yes. The 8259 PIC (interrupt controller) is fully programmable for edge
and level. It's possibel to go from edge to level on a common PC but you
have to write your own drivers and other drivers would blow up.

<Are all PS/2 s level-triggered or only the MCA ones?

Only MCA.

Received on Wed Dec 30 1998 - 17:48:28 GMT

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