> Well, the 650x is a VERY thrifty architecture. It has no memory-to memory
> operations, nor does it have any operations involving more than one register
> at a time.
TXA ? (Don't kill me :)
[...using 'only' one ALU...]
Not uncommon back than and very efficient. I still belive the 65xx
is one of the best - the instruction set is well defined to get
the maximum out of a minimal hardware. You can see the function
blocks klick just by looking at the instructions.
> [... about resources]
Exact, thats the main Problem with most %used numbers.
> I've taken a good hard look at implementing the 6500 core in XILINX and find
> that performance, which is VERY much of interest, is impacted most by ALU
> design. Now, the Virtex CLB allows a single CLB to function as a two-bit
> full-adder. If one wants the best performance/resource allocation tradeoff,
> I'm nearly convinced that the best way might be to design it with a 2-bit
> ALU slice because the resource consumption is small yet the delay for a
> 2-bit registered implementation of an 8-bit ALU would be just as fast as an
> 8-bit implementation because of the carry delay from stage to stage. It
> appears to me that the rate-determining step, then, becomes how fast a clock
> can be routed through the array. In the case of the 2-bit slice, it doesn't
> have to propagate very far to get the job done.
Well, after all, any serious attempt to bring a 6502 into a FPGA
will be about speed - and saving resources might not be the
primary goal.
> With an 8-bit
> implementation, there's a lot more routing delay, and at least four times as
> much delay per cycle in order to allow the carry to settle. Since the ALU
> is used more than once per machine cycle . . . (see where all this leads?)
More than once ?
Maybe I'm just blind, but I cant see more than one ALU op per cycle.
Gruss
H.
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Ich denke, also bin ich, also gut
HRK
Received on Fri Aug 27 1999 - 15:45:03 BST