Whether this is correct or not, the real problem lies in that the data is
available in the clear by virtue of the fact the unmodified data travels
into the FPGA in a predfined way, allowing a simple and direct copying
process to be set up. No reverse engineering is needed, just a rote copy.
Dick
-----Original Message-----
From: Tony Duell <ard_at_p850ug1.demon.co.uk>
To: Discussion re-collecting of classic computers
<classiccmp_at_u.washington.edu>
Date: Sunday, August 29, 1999 1:05 PM
Subject: Re: PDP era and a question
>> > Anyway, the real point is that certainly for Xilinx FPGAs, if you buy
the
>> > official tools you get a program to 'reverse engineer' a bitstream back
>> > to the CLB map. Converting that to a schematic is still a non-trivial
task...
Received on Sun Aug 29 1999 - 23:19:04 BST