Hi all,
I have recently joined the list, not yet contributed too much, but enjoyed
reading quite a bit.
My personal preference is older stuff - if it contains integrated circuits,
I am not too much interested (with the possible exception of a Cray-1).
I did not succeed in finding any serious equipment in vacuum-tube technology.
Therefore, I decided to design and build a complete computer with
vacuum-tube technology from scratch. A short description of the project is
enclosed,
for those of you who might be interested. The attachment is best viewed with
some straight ASCII editor, like the MS-Editor.
Thanks to Hans Franke for a reading of a draft version and constructive
comments.
BTW, I am located in Munich, Germany.
John G. Zabolitzky
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Project MUNIAC Rev. 1.0 of May 29, 1998
============== Rev. 1.1 of Jan 25, 1999
Rev. 1.2 of Jan 30, 1999
John G. Zabolitzky
Overview
--------
MUNIAC is a complete general-purpose digital computer built
with vacuum-tube technology. It is NOT a replica of any known
specific historic machine. It is designed and built using
technology available (at least in principle) around 1959.
MUNIAC is designed from scratch. The idea is that by limiting
myself to 1959 technology I will retrace the paths of thought
traversed by the designers of those times.
The name MUNIAC originates from the historic pattern for names
of early computers <location abbreviation>IAC, where IAC stands
for Integrator And Computer. Such early names were e.g. ILLIAC
for Illinois Integrator and Computer, etc.
By "available in principle" I wish to state that for cost
reasons actual historic parts will be used only where
reasonably available. Most parts used will be of modern
manufacture. For example, modern silicon diodes will be used
which do have better data than diodes available in 1959,
but logically do not differ very much. In particular, the
most hurting parameter, capacity, is very much the same today
as it was then, at 1 pF.
The date of 1959 is chosen since the end of the vacuum tube
era is intended. Any later date would imply a tendency towards
transistors instead of vacuum tubes, any earlier date would
make the technology distinction rather subtle.
Basic design
------------
MUNIAC is a 12 bit parallel computer. Memory is of course the
most relevant decision; magnetic core was selected as
appropriate for the time as well as feasible today.
The 12 bit word size is due to availability of memory,
overall machine cost and size limitations.
The actual memory used is a core stack from a
Digital Equipment PDP-8e machine, 4 k words of
12 bit each. I was fortunate to purchase a new-old-stock
PDP-8e together with an extra memory plane and
complete engineering documentation, giving all the currents,
voltages, and timing. This was manufactured probably
in 197x and could perform at 1.4 ęsec cycle time.
The machine was built with 74xx SSI devices,
power transistors as core drivers. Only the core
stack itself will be used in MUNIAC, none of
the associated electronics. While the cores are
quite smaller and faster than those of 1959, the
principle is the same, and with vacuum tube drivers
the core will be much slower, of course.
There is no backup storage, like drum, disk, tape.
Apart from registers (see below) core memory is
the exclusive storage device. I/O is a Siemens
teletype with papertape-reader/-punch, of around
1957, running at a speed of 50 baud. This is the
only periphery. Papertape (European style 5 channel)
could be viewed as external storage, however.
The CPU designed around the core stack has 5 registers:
operation register, operand register, accumulator,
memory address register, and program counter. Out of
these only two are visible to the programmer:
accumulator and program counter. There is no
index register, nor any hardware provision for
indexing.
Program code is 24 bit wide, i.e. each operation
occupies two 12 bit words. The first word is the
opcode, the second word is
a. the address or
b. an immediate value
The style is "long instruction word", i.e. relatively
little decoding is done, most functional unit
control lines come directly from the opcode with only
little gating involved. That makes the number of
instructions (if counted the classical way) rather large,
and the machine hardware rather simple since little decoding
as well as little control logic is required.
MUNIAC is a single address machine. Basic opcodes are
LOAD address
LOAD immediate
STORE address
STOREcond address
JUMPcond address
ALUOP immediate
ALUOP address
For simplicity operations are microcoded. There are only four
different operations, as far as microcode is concerned:
STORE, JUMP, ALUOP immediate, ALUOP address. LOAD is a special
case of ALUOP.
A small diode matrix is used as microprogram storage, less
than 32 words of less than 22 bits wide are used (This
part of the design not definitely concluded yet).
I/O will be implemented as special cases of
LOAD (IOREAD), STORE (IOWRITE), and JUMPC (IOTEST).
The machine is designed to be "very" von Neumann.
This is because usually I design strongly Harvard-
Style, with very independent program and data
pathes. Since there is only one single core stack
intended, that was out of the question. Since the
machine therefore is von Neumann style, I decided
to emphasize that feature. Indexing is to be performed
by using a program word as index register, i.e.
incrementing the address in LOAD address, for example.
Similarly subroutine return jumps are executed by
writing the return addres after the JUMP opcode.
In other words, program modification by the program
itself is used extensively.
Basic hardware elements
-----------------------
Three 19" racks are used. The bottom of each rack
holds the power supplies (good old Seymour style),
the upper parts a total of about 30 card cages for
standard Euro cards 100 mm x 160 mm. Each cage can
hold up to 14 cards. Standard 19" mechanical
components are used for cost and availablity
reason. Ventilation is by off-the-shelf 19"
ventilator assemblies.
There are four types of cards:
a. logic and registers (approx. 200 used)
b. clock drivers (approx. 25 used)
c. core sense amplifiers (12 used)
d. core drivers (19 used)
Types a,b use the same printed circuit board, differing
parts mounting. Types c, d are different.
The tubes used have been selected according to
availability of surplus stocks. Starting from
surplus stock lists, the most suitable tube for
each purpose has been selected, resulting in average
cost of less than 1 US$ per tube.
Types a and c use 6BQ7A miniature dual triodes,
two per card, approx. 400 tubes total.
Type b uses 6CW5 miniature power
pentodes, two per card, approx. 50 tubes total.
Type d uses 40KG6 beam power pentodes, four per card,
76 tubes total.
The cards plug into DIN41612 wire-wrap connectors,
i.e. the back of the 19" rack is a wire-wrap plane.
All supply and signal connections are done
as wire-wrap.
One big decision to take is the design of the logic
implementation. For cost and size reasons I decided
NOT to use cathode-followers, but straight diode
and-or-invert gates exclusively. One card type a holds
four sections, each of which consists of one triode
as inverting amplifier, with the grid connected to
a two-level and-or diode network. That would
correspond to "diode-transistor-logic" (DTL) as
opposed to using cathode followers wich would make
the logic similar to emitter coupled logic (ECL).
The machine therefore will be rather slow,
memory cycle time about 20 ęsec. Using cathode
followers would give a significant speed increase,
but also would increase size and power by at least
a factor of 1.7.
Thus there is only ONE gate type used for implementation
of ALL logic and registers: the and-or-invert gate.
Typical width of the or is 2 to 5, typical width of the
and is 1 to 6. The card layout is such that a total of
32 inputs can be distributed in many different ways over
the four gates on that card, by mounting the diodes
properly. Each card has 4 outputs, corresponding to
the four gates or four triode systems.
A latch is formed by cross-connecting two of the basic
gates, a master-slave flip-flop by using two latches,
i.e. four gates, i.e. one card. By using a few more
of the and-or functionality available anyway, the master-
slave flip-flop can also be a counter bit, only little
extra carry-look-ahead logic is required. Therefore,
a 12 bit register or counter occupies one of the card
cages.
The entire logic design is parallel register transfer
with fixed central master clock. Therefore, the
design task is rather well structured, essentially
NO irregular pieces, therefore straightforward
design verification.
Power consumption will be 4000 watts approximately.
There are 24 V heater supply ( 4 x 6.3 V, 1000 watts),
80 V heater supply ( 2 x 40 V, 700 watts ), DCplus 230V
supply (2000 watts), and DCminus 200V (300 watts) supply.
Current Status
--------------
As of Jan 25, 1999 most of the design is completed.
All non-standard parts are in house, printed
circuit boards have been manufactured. Power supplies
have been built and tested OK. The first few card cages
have been constructed; about 50 cards built
and tested up to now.
Total parts cost is estimated at DM 30.000,-.
Total time required is estimated at about 2
years remaining (less than 20 hours/week can
be used; one and a half year so far is in design and
construction up to this point).
Received on Sat Jan 30 1999 - 07:02:02 GMT
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