8080A I/O Pin?

From: Allison J Parent <allisonp_at_world.std.com>
Date: Tue Jul 13 18:16:04 1999

<What pin does the 8080A (raise/lower?) to indicate
<that it is doing an I/O read/write instead of a memory
<read/write? Also, does anyone have a copy of the IMSAI
<MPU-A Rev-4 schematics that they could scan and send me?

Your thinking 8085... 8080 is very different.

There are two pins on the CPU:

        WR/ (pin 18) indicates precessor write (memory or IO).
        PDBIN (pin 17) indicates a IOREAD, MEMORY READ, INSTRUCTION FETCH

The latched 8bits from the data bus at Sync(pin 19) time tell if the
operation is

 D0 SINTA Status interrupt acknowledge
 D1 SWO Status write out
 D2 SSTACK Status Stack operation
 D3 Shlta Status Halt acknowledge
 D4 Sout Statue output (IO output operation commences)
 D5 SM1 Status M1 state (instuction fetch)
 D6 SINP Status input (IO input operation commences)
 D7 Smemr Status memory read

Those status signals only indicate the next bus cycle activity and must be
cates with Sync (psync on the bus), PDBIN, WR/ before the whole mess makes
sense. Intel later created the 8228/38 chips to do this. Otherwise it
takes a good handful of gates to sort it out.

I have the Bursky book, no scanning ability. if you can altair docs the
8080 and 8212 status latch portion of the altair CPU are the same.


Allison
Received on Tue Jul 13 1999 - 18:16:04 BST