Rebirth of IMSAI

From: Dwight Elvey <elvey_at_hal.com>
Date: Tue Mar 30 15:40:19 1999

ard_at_p850ug1.demon.co.uk (Tony Duell) wrote:
>
> The problem with the 8080 is that it always started executing at location
> 0 after a reset. So on the Intellec MCS8i, they put _RAM_ at location 0
> (which could, of course be loaded from the hardware frontpanel). Then you
> put a jump instruction at location 0, hit reset and started the CPU.
>
> So, of course, a lot of 8080 applications/OSes assumed RAM at location 0.
> So on a machine without a frontpanel, you had to have some way of mapping
> some kind of 'ROM' into the first 3 locations that would get the CPU to
> jump to the real ROM at the top of memory. And then map out the 'ROM' and
> replace it with RAM.
>
> I said 'ROM' because on a number of machines, it was just a few TTL chips
> that gated C3, lobyte, hibyte onto the data bus on the first 3 fetches
> after reset.

Hi
 It isn't too hard to rig the processor to have the ROM
doubled into the low address locations during the first
few instructions. I've also rigged up several processors to boot
from a ROM that would copy themselves into RAM at the same
address and then switch out the ROM to be running completely
from RAM and all of its flexability. Booting from any fixed
location is a pain in a larger processor but needed for
simple controller applications. I've always felt that it
would be better for the reset to work just like an interrupt
that had some external hardware to supply the boot address.
On larger systems, the additional hardware is minimum and
there is a lot of added flexability.
Dwight
Received on Tue Mar 30 1999 - 15:40:19 BST