ENIAC-on-a-Chip

From: Derek Peschel <dpeschel_at_u.washington.edu>
Date: Sun May 30 00:05:10 1999

> There are various systems like this. The most common (in my limited
> experience) being a JTAG boundary scan. Basically, some LSI devices have

The system Tera uses is quite similar, except that it extends to the interal
circuitry of the chip rather than just the boundary (pins) of the chip.

-- Derek
Received on Sun May 30 1999 - 00:05:10 BST