ENIAC-on-a-Chip

From: Allison J Parent <allisonp_at_world.std.com>
Date: Sun May 30 11:24:30 1999

<> There are various systems like this. The most common (in my limited
<> experience) being a JTAG boundary scan. Basically, some LSI devices have
<
<The system Tera uses is quite similar, except that it extends to the intera
<circuitry of the chip rather than just the boundary (pins) of the chip.

Look again. They are likely the same thing. Most boundary scan approaches
allow not the pin level output but a snapshot of the core logic to be
brought out as a serial bit stream on just a few pins. It is an
approximation of the PDP-8 style front pannel where most of the internal
working can be seen in lights and allow diagnosing say a stuck bit in the
ACC or core.

Allison
Received on Sun May 30 1999 - 11:24:30 BST