OT: how big would it be?

From: allisonp_at_world.std.com <(allisonp_at_world.std.com)>
Date: Wed Oct 20 11:12:59 1999

> These days, no one would seriously attempt to build a CPU equivalent using
> TTL SSI/MSI components simply because the packaging gets too much in the way
> of smooth data flow. I once built a 650x CPU equivalent on a 4"x6" wirewrap
> board using TTL SSI/MSI, but it was my goal to build one using the logic
> available to the original designers. That was not easy, but it fit only
> because of the efficiencies inherent in the 650x series timing and
> instruction set.

Impressive. I'd love to see that design.
 
> If one were to do the same thing with an 8080 CPU design, I suspect it could
> be forced to fit on a board like an S-100 card. It might be difficult to do
> in "period" family logic, i.e. with the parts that were available to the
> designers of the 8080, though. If you'd like to convince yourself of this,

The 8080 was emulated using the 300x bitslice chip set. The 300x was a
2bit wide slice. the board was much larger than S100 form factor.

> take a look at the '72 TTL data book from T.I. or Signetics. If one were
> limited to 28-pin FPLD's and smaller, I think it could be done easily

Since I have the Signetics '71 data book and also the '72 ti data books
that is very true.

> enough. That would take the emphasis off parts search and the occasional
> unavailability of some functions, while allowing some random logic to be
> localized in a single device rather than requiring several different flavors
> of AOI gates, expanders, etc. The internal data paths of the 8080 could

The tricks were sometime burried in things like open collector wired OR
logic that made system like the PDP-8E rather than tristate.

> I personally think it would be fun to build an S-100 card to replace the
> 8080 LSI. It might well be possible to replace all the external support
> logic with the hardware that goes "inside" the device, and you could fiddle
> with the instruction set more or less like the folks with wire-wrapped PDP8
> processors did from time to time.

We, having done that with 290x stuff the 8080 was weakest in not having an
orthoginal instruction set. the best example was LXI SP, load SP with
immediate but, there was no store SP at all. To save the SP(stack
pointer) you had to save HL pair, Load it with 0000, add SP,HL and then
you could store the result from the HL pair. YUCK! With holes like that
filled the z80 really was an improvement.

Allison
Received on Wed Oct 20 1999 - 11:12:59 BST