Central Point Option floppy controller

From: Eric Smith <eric_at_brouhaha.com>
Date: Wed Sep 15 15:54:41 1999

Dave McGuire <mcguire_at_neurotica.com> wrote:
> Hell, big PICs like the 17C54 run at 33MHz, at damn near 1 avg ins/cycle,
> too. I'm *sure* it could be done with a PIC.

No, at 4 or 8 clock cycles per instruction, unfortunately.

Microchip claims that their chips are "pipelined", but they don't understand
the meaning of the word. They divide down the clock into four internal
phases, for instruction fetch, operand read, ALU, and result writeback.
This is documented in some of their data sheets.

In a truly pipelined CPU, they would do the operand read for instruction
n+1 at the same time as the ALU operation for instruction n and the
result writeback for instruction n-1.

Actually, although they don't describe it that way, I think that they
do a limited sort of pipelining, in that I think they actually use all four
clocks for each instruction fetch, and just latch the result on phase 1.
That way their ROM doesn't have to be as fast.

The Scenix SX18 and SX28 parts, which are enhanced clones of the PIC16C5x
family, have a "turbo" mode that is fully pipelined, so most instructions
really do run in one clock cycle (rather than four). Also, they run at
up to 100 MHz. They would be much more suitable for implementing a
floppy disk controller.
Received on Wed Sep 15 1999 - 15:54:41 BST