It could be a microcontroller project, but it's easy enough if you use a
relatively small CPLD. What's critical is that you need a VCO or some
digital analog to it which causes the counters to run more quickly while the
beginning track to ending track difference is large and ramps up slower than
it ramps down. I'd not depend on that, since each drive will be different.
It's best done, IMHO, if one uses a drive-resident circuit with slew rates
tuned to the individual drive. Thos of us who can't remanufacture our
drives NEED this in order to make our 8" drives stay well. I
microcontroller could handle the job fine if it just could be adjusted with
a pot rather than having to have parameters experimentally determined and
then fit via cut-and-try.
Dick
-----Original Message-----
From: Al Kossow <aek_at_spies.com>
To: classiccmp_at_classiccmp.org <classiccmp_at_classiccmp.org>
Date: Friday, February 04, 2000 2:51 PM
Subject: Re: WD1770 help needed
>"In the case of the 1771 and 179x series it's possible to build a really
neat
>circuit I've seen but never tried to match, which uses the /TEST pin on the
>FDC to cause the device to put out its pulses much faster, allowing them to
>be accumulated externally in a counter, which, drives a DAC which drives a
>VCO, which drives the counter as it downcounts the number of steps, thereby
>slewing the head assembly. This could lead to an interesting but lengthy
>discussion.
>"
>
>Sounds like an ideal candidate for reimplementation in a single chip
>microcontroller.
Received on Fri Feb 04 2000 - 21:08:28 GMT