On Tue, Feb 29, 2000 at 05:44:47PM -0500, r. 'bear' stricklin wrote:
> On a tagged architecture, instruction data includes 'tag' bits which are
> used to type the data, and allow runtime data checking in hardware. SPARC
> processors use a tagged architecture.
Seems like a good idea. But there would be a limited fixed set of types
available then.
>
> The "multiple caches" goes beyond the instruction and data caches common
> today.
>
> "Major caches are the Stack cache, the Memory Map cache, and the
> Instruction cache." Of these, the memory map cache is the one I find
> unique; it's an 8K (sic) RAM which "cross references the virtual page
> number and the physical page number". The instruction cache is part of an
> optional "Enhanced Performance" unit which I don't have, and also seems to
> be where the pipeline (three-stage) is implemented.
Hmmm, wouldn't any MMU have to keep track of the virtual-to-physical
mapping? Would it normally just do it in main memory if there isn't
usually special cache for that?
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Received on Tue Feb 29 2000 - 17:45:07 GMT