Tim's own version of the Catweasel/Compaticard/whatever

From: Richard Erlacher <richard_at_idcomm.com>
Date: Wed Jul 5 11:40:57 2000

You've raised a valid point, but it hinges on the amount of effort involved,
not on the details of the hardware. If you use a 44-pin CPLD programmable
in-circuit by means of a parallel cable, you have to hook up the CPLD, which
means 44 wires, and you have to hook up the RAM, but that's part of the 44
wires, AND you have to hook up the host interface, but that's part of the 44
wires, and you have to hook up a few of the lines to the FDD, but that's
part of the 44 wires. So, aside from power and ground, you have about a
dozen wires to the parallel port, a half dozen to the FDD, and two dozen to
the RAM, of which,say 8 are shared with the host adapter port. Those are
two levels, so that's an additional 8 wires. (now, I'm just guessing here)
Given that you have the same logic in TTL SSI and MSI parts, e.g. counters,
latches, gates, I'd say you'll have the same connections to the "outside"
and at least twice as many for the inside. What's more, the required power
will be considerably greater. If you provide sufficient capacitors on the
board, the CMOS CPLD can probably run from the power it draws from the two
outside sources, in fact probably from the pullup resistors on the FDD
cable. The TTL won't do that. If you go with HCMOS that might work with
the same source of power, but now you won't be able to dig them out of the
old parts bin.

If the CPLD is designed using the FREE software on the XILINX website, the
schematic will be drawn in primitives, since the CPLD libraries don't
contain the same features as the FPGA libraries. That will limit the
ability to use the same schematic. With a little effort, the same logic
could be implemented in both technologies, however. The SSI/MSI board will
be considerably larger, though. A board for the CPLD version would be
barely large enough to support the connectors.

I guess you'll have to weigh the alternatives yourself.


----- Original Message -----
From: John Honniball <John.Honniball_at_uwe.ac.uk>
To: <classiccmp_at_classiccmp.org>
Sent: Wednesday, July 05, 2000 9:53 AM
Subject: Re: Tim's own version of the Catweasel/Compaticard/whatever

> Just a thought about the CPLD vs. TTL discussion: Would it
> be possible to design the device such that it could be
> built EITHER in TTL chips OR as a CPLD? With the same
> interface to the host computer and software? If it could,
> then those who prefer CPLDs could use one, and those who'd
> rather rummage about in the "500ft" junk box can do that.
> Or am I missing an fundamental difference here?
> --
> John Honniball
> Email: John.Honniball_at_uwe.ac.uk
> University of the West of England
Received on Wed Jul 05 2000 - 11:40:57 BST

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