Defining Disk Image Dump Standard

From: John Wilson <wilson_at_dbit.dbit.com>
Date: Sun May 28 18:42:39 2000

On Sun, May 28, 2000 at 10:38:55PM +0000, Mark wrote:
>The Catweasel disk controller hardware (available as an ISA card for PCs) is
>capable of similar things. However due to its developer (stupidly IMO)
>refusing to release details on how to program it directly, this would be of
>no use; you're stuck with the provided drivers which are apparently pretty
>poor.

I thought he had changed his mind about this? When I first talked to him
he seemed pretty paranoid, but I think he eventually realized that there's
not a big enough market for there to be even a point in stealing his idea
and competing with him (although, I sure hope he's done a PCI version by
the time ISA slots disappear entirely). I certainly remember that he
softened his position about this, but I don't know if that turned into a
manual. Then again, the CW/ISA board comes with no manual anyway!

Anyway I sorted out a lot of the Catweasel/ISA details, from disassembly and
the few sources that were available when I was doing it, it might be enough
to write a driver (I've gotten stuck with my own work on RX01 and RX23 style
drivers, I can read data enough of the time to think I'm really close but it
works less than half the time).

Here's what I've worked out on the I/O ports (default base is 320h):

base+0 autoincrementing memory I/O port (reads/writes next byte from buffer)

base+1 read (and ignore value) to clear address counter
        write 0 (or any value?) to stop I/O (w/o touching addr ctr)

base+2 raw floppy disk control/status signals
        (N.B. IOR and IOW are two different regs)
        write:
        b7 MO1 (0=asserted)
        b6 ???
        b5 DS0 (0=asserted)
        b4 DS1 (0=asserted)
        b3 MO0 (0=asserted)
        b2 HEAD (1=head 0, 0=head 1
        b1 DIR (1=out, 0=in)
        b0 STEP (1=asserted)

        read:
        b5 DSKCHG (0=asserted)
        b4 TK00 (0=asserted)
        ... don't know the others (INDEX is probably here too)

base+3 MSB gives access to a shift register I think???
        (selected by addr ctr to must touch base+0 to advance)
        seems to be config bits (you can read 16 bits, don't know if they're
        the same ones you write or just hard-wired version bits):

        index 0=0 to select high-speed clock
        index 2=0 to make index pulse not appear in data stream

        I forget why I think I know that, no idea about other bits (my code
        writes 0 to 0&2 and *almost* works)

base+4 ???

base+5 write 0 (or any value???) to start writing to disk (?)

base+6 ???

base+7 read to start reading from disk

The board has a RAM which is indexed by the hidden counter (cleared when
base+1 read), each IN or OUT to base+0 reads/writes a byte and increments
the counter. The value stored in each byte is the amount of time (counted
from a high-speed internal clock, I forget the data rate) between transitions
on the head data. When reading, this value fits in 7 bits, I don't know how
guaranteed that is (maybe they just assume that the transitions will always
come soon enough), but the routines I looked at would enable reading for
something a bit over one track time, and then write 80h to base+0 to mark
the end of the track data (I guess it's the same address counter for both
base+0 accesses and data written into RAM by the board itself), which the
decoder routine would depend on.

I haven't even tried to write a "write" routine yet, but IIRC the interval
timer still counts up rather than down, so the durations stored in RAM have
to be negated. Normally you rewrite the whole track, since the CW isn't too
fancy about searching for sector headers (I think it's supposed to be able
to find one of the System/34 marks but it's not a general-purpose feature,
anyway I don't know how to trigger that).

John Wilson
D Bit
Received on Sun May 28 2000 - 18:42:39 BST