On Sun, 8 Apr 2001, Tony Duell wrote:
> > > Oh, right. I wondered if it did... Incidentally, is the ESDI spec
> > > available anywere (or at least a signal description)?
> >
> > To what level of detail, Tony? I have a copy of the Maxtor Product Spec
> > and OEM Tech Manual for the XT-8000E/EH drives that I can extract some
> > information from.
>
> Well, to start with, a pinout and a brief description of the signals (as
> in : DS0-DS2, drive selects, binary coded, 000 = no drive selected).
>
> I don't really need this, it's just that it's an interface I know nothing
> about and think that should be changed :-)
First off, the drive pinouts are as follow:
ESDI HARD DRIVES
HEAD SEL. 3 2 1 GND
Though ESDI and ST506/412 drives HEAD SEL. 2 4 _ 3 |
share similar looking cables, WRITE GATE 6 5 |
even to the point of having a CONFIG/STAT DATA 8 7 |
twist, the actual data and con- TRANSFER ACK. 10 9 |
trol signals are very different. ATTENTION 12 11 |
One should never mix components HEAD SEL. 0 14 13 |
from these two drive types. SECT/ADD.MK. FOUND 16 15 |
While the ST506/412 interface HEAD SEL. 1 18 17 |
utilizes a standard pulse code INDEX 20 19 |
to transmit data between the READY 22 21 |
drive and controller, ESDI uses TRANS.REQUEST 24 23 |
a pulse code that does not require DRIVE SEL. 1 26 25 |
the level to return to zero between DRIVE SEL. 2 28 27 |
pulses. This format is refered to DRIVE SEL. 3 30 29 |
as NRZ, or Non Return to Zero. By READ GATE 32 31 |
utilizing NRZ, the clock that data COMMAND DATA 34 33 GND
is transfered by can be increased,
thereby increasing the throughput to
and from the ESDI disk.
DRIVE SEL'D 1 2 SECT/ADD.MK. FOUND
SEEK COMPLETE 3 _ 4 ADDRESS MARK ENABLE
RESV'D FOR STEP MODE 5 6 GND
WRITE CLOCK+ 7 8 WRITE CLOCK-
CARTRIDGE CHANGED 9 10 READ REF. CLOCK+
READ REF. CLOCK- 11 12 GND
NRZ WRITE DATA+ 13 14 NRZ WRITE DATA-
GND 15 16 GND
NRZ READ DATA+ 17 18 NRZ READ DATA-
GND 19 20 GND
Note: The above is copied from TheRef v4.3.
>From the Maxtor XT8000E/EH Product Specification & OEM Technical Manual
4.2 Drive Selection
Drive selection occurs when the controller places the address of
the drive to be selected on the three drive select lines. See
Figure 4-2, Drive Select Circuit, and Table 4-1, Drive Selection
Matrix. Only the selected drive responds to the input signals,
and only that drive's output signals are gated to the
controller. The details of setting the drive selection jumper
are covered in section 8-1, Drive Address Selection Jumper.
--------------------/\/\/\----------
| |
| ----------------/\/\/\---------|---- +5v
| | |
| | ------------/\/\/\----------
| | |
| | | _________
| | | |Decoder|
| | | | 0|- N/C
| | | | |
--------+---------------| 1|--+ \
Drv Sel 1 | | | 2|--+ |
| | | 3|--+ |
------------+-----------| 4|--+ |-- Drive Selected
Drv Sel 2 | | 5|--+ |
| | 6|--+ |
----------------+-------| 7|--+ /
Drv Sel 3 |_______|
Figure 4-2
Drive Select Circuit
Drive Drive Drive
Drive Select Select Select
Selected 3 2 1
--------------------------------
None 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
--------------------------------
Table 4-1
Drive Selection Matrix
The referenced Table 8-1 merely cites the correspondence of the drive
selected and the DSn jumper, where 1=1, 2=2, ... 7=7.
======================================================================
That is about all it covers.
- don
Received on Mon Apr 09 2001 - 01:21:56 BST
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