On December 12, Richard Erlacher wrote:
> If it topped out at 7 MBps, it was probably because the bus handshake was
> clocked with a CPU clock, in order to ensure the CPU would "see" the
> transitions.
I am reminded of my favorite piece of broken english, found in a
Taiwanese PeeCee motherboard manual many years ago:
"If use 387 coprocessor, the clocked by CPU clock."
No, I made no typos there. :-)
-Dave
--
Dave McGuire
St. Petersburg, FL
Received on Thu Dec 13 2001 - 00:34:07 GMT