MITS 2SIO serial chip?

From: Peter C. Wallace <pcw_at_mesanet.com>
Date: Sun Dec 16 11:58:52 2001

On Sun, 16 Dec 2001, Richard Erlacher wrote:

> I disagree that it's a mess. I haven't looked at the requirements for a Z80
> peripheral since the early '80's, but I can assure you that I'd dispose of any
> 1st year engineering intern who couldn't whip up a suitable PAL or equivalent
> MSI/SSI logic to handle the generation of properly timed inputs to the thing in
> an hour or less.


Sure its trivial to do now but we were talking 1981 when PALS were
expensive.



>
> See below, plz.
>
> regards,
>
> Dick
> ----- Original Message -----
> From: "Peter C. Wallace" <pcw_at_mesanet.com>
> To: <classiccmp_at_classiccmp.org>
> Sent: Saturday, December 15, 2001 9:03 PM
> Subject: Re: MITS 2SIO serial chip?
>
>
> > On Sat, 15 Dec 2001, Richard Erlacher wrote:
> >
> > > That's what clocks are for. As I wrote before, you derive the /IORQ from
> the
> > > /IOR and /IOW, build your select from those as well, and then use a
> registered
> > > output for the /RD signal. The default bus clock is 8 MHz, and the default
> for
> > > the -A SIO/DART is 4. That should provide enough setup time.
> > >
> > > Dick
> > But that violates the DART timing, you have to delay IORQ till after the
> > RD signal is valid, but how do you know you even have a IO read cycle
> > till you get the IORD strobe...
> >
> My point was that, with a PAL, you can decide what timing you want and produce
> it from the ISA signalling protocol, regardless of the specifics. It's not
> rocket science. The presence of either /IOW or /IOR tells you there's an IO
> cycle in progress. If you register that negative logic NOR (the equivalent of a
> 2 input NAND, in this case) you can then register the output and feed that
> forward to create the required strobes in whatever order you see fit.

Except that you only have the 4.77 Mhz clock (not 8 as you specified
earlier) to generate all timing so if you delay the IORQ by one clock you
only have 200 nS IORQ width, which violates DART timing. I suppose you
could generate a wait state, or have a higher speed asychronous clock do
the timing, but as I said before: messy...


>
> Writing the equations, compiling them, and programming the PAL should take no
> more than 5 minutes. That's a lot less time than figuring out what you can do
> with unused SSI components already on the board, if there are any, so, from that
> standpoint, it's just economics. It's no accident that the select and enable
> timing to the 8250 on most I/O boards was also done with a PAL

Sure decode can be done with a PAL, but the 8250 requires no messy state
machine or wait states to recreate Z80 bus timing, just a pure
combinatorial decode...


> >
> > Like I said before, a mess...
Still a mess...

> >
> >
> >
> > >
> > > ----- Original Message -----
> > > From: "Peter C. Wallace" <pcw_at_mesanet.com>
> > > To: <classiccmp_at_classiccmp.org>
> > > Sent: Saturday, December 15, 2001 10:33 AM
> > > Subject: Re: MITS 2SIO serial chip?
> > >
> > >
> > > > On Sat, 15 Dec 2001, Richard Erlacher wrote:
> > > >
> > > > > Well, that doesn't change the fact that if you AND /IOR with /IOW you
> get a
> > > > > useable /IORQ. Whether you feed the /IOW forward doesn't matter.
> > > >
> > > > Except that you need to have a valid read signal before IORQ...
> > > >
> > > > >
> > > > > I stand corrected on my presumption that the M1 and IORQ were used
> solely
> > > for
> > > > > the int handshake. I never liked the Z80 peripherals and never even
> once
> > > used
> > > > > one in my own work, though they were everywher in commercial hardware.
> Even
> > > my
> > > > > HP plotter has one it it, though it doesn't have a Z80.
> > > >
> > > > Actually I thought the Z80 peripherals were quite nicely
> > > > integrated with the Z80, with the status affects interrupt stuff, daisy
> > > > chained interrupts and other nice ideas. (many of which had been done
> > > > before in minicomputers) They also had consistant reset polarity's and
> > > > basically look like they gave a lot of thought to System Design, not just
> > > > chip design. When we moved from designing Z80 stuff to embedded PC stuff
> > > > it was like going back to the stone ages. The Intel stuff being a rag-tag
> > > > pile of ****
> > > >
> > > > The Z8000 stuff was even nicer, with Multiplexed data/address bus
> > > > so the all peripherals could have 256 directly addressed registers without
> > > > losing valuable pins on the 40 pin chips...
> > > >
> > > Well ... we digress ... I never liked the Z-80 setup because the peripherals
> > > basically limited the CPU speed, and I liked the Z8000 series even less,
> though
> > > I don't remember why. I didn't EVER use an Intel product (other than at the
> > > board level) until the 80186 came out, BTW.
> > > > >
> > > <snip>
> > > > >
> > > > > Dick
> > > > >
> > > > > ----- Original Message -----
> > > > > From: "Peter C. Wallace" <pcw_at_mesanet.com>
> > > > > To: <classiccmp_at_classiccmp.org>
> > > > > Sent: Saturday, December 15, 2001 8:38 AM
> > > > > Subject: Re: MITS 2SIO serial chip?
> > > > >
> > > > >
> > > > > > On Fri, 14 Dec 2001, Richard Erlacher wrote:
> > > > > >
> > > > > > > I don't think the DART would have been such a mess. If you AND
> (/IOR
> > > and
> > > > > /IOW)
> > > > > > > you get a useable IORQ, not that you really need it, since it's only
> > > used in
> > > > > > > conjunction with M1 to signal the mode-2 interrupt acknowledge,
> which
> > > > > wouldn't
> > > > > > > occur in this case. If the device is selected I'm not at all sure
> it
> > > cares
> > > > > one
> > > > > > > iota whether IORQ is active.
> > > > > >
> > > > > > Not true, the DART like the SIO has no write signal...
> > > > > >
> > > > > > >
> > > > > > > see below, plz.
> > > > > > >
> > > > > > > Dick
> > > > > > > ----- Original Message -----
> > > > > > > From: "Peter C. Wallace" <pcw_at_mesanet.com>
> > > > > > > To: <classiccmp_at_classiccmp.org>
> > > > > > > Sent: Friday, December 14, 2001 6:45 PM
> > > > > > > Subject: Re: MITS 2SIO serial chip?
> > > > > > >
> > > > > > >
> > > > > > > > On Fri, 14 Dec 2001, Richard Erlacher wrote:
> > > > > > > >
> > > > > > > > > <snip>
> > > > > > > > > > Dart is Z80 bus, (like an Async only SIO) not Intel. Have to
> take
> > > your
> > > > > > > > > > word on the TCM78808 - sure it was available in 1981?
> > > > > > > > > >
> > > > > > > > > My old TI datasheets are hiding, so I can't verify what was
> when.
> > > > > > > > >
> > > > > > > > > I'm not sure exactly what difference it makes whose bus the
> serial
> > > I/O
> > > > > chip
> > > > > > > is
> > > > > > > > > designed for when the whole bunch of devices use essentially the
> > > same
> > > > > > > signals to
> > > > > > > > > get the job done. The DART doesn't work much differently than
> any
> > > other
> > > > > > > serial
> > > > > > > > > I/O device so long as you don't attempt to use some of its
> unique
> > > > > features.
> > > > > > > It
> > > > > > > > > seems to me that it takes about the same quantity of
> machinations to
> > > > > make
> > > > > > > the
> > > > > > > > > 8250, which is also not ideally suited to the ISA bus, work on
> the
> > > ISA
> > > > > bus,
> > > > > > > as
> > > > > > > > > it would take to make a Z80 DART or an 8251 or a 2651 do the
> job.
> > > > > Likewise
> > > > > > > for
> > > > > > > > > the 2681/68681. No matter what you need, a small PAL will do
> the
> > > trick.
> > > > > > > That
> > > > > > > > > certainly wasn't lost on I/O board makers.
> > > > > > > >
> > > > > > > >
> > > > > > > > The 8250 is a direct ISA bus interface (no logic other than decode
> > > needed)
> > > > > > > > The DART would be a mess, using the Z80s M1,IORQ and all that.
> (not
> > > that
> > > > > > > > there's anything wrong with the Z80 way)
> > > > > > > >
> > > > > > > Not exactly direct. you do have to invert the ALE to form the
> > > DataStrobe or
> > > > > > > whatever that signal was. I always liked the 8250 because it was a
> > > 1-part
> > > > > > > solution to a problem otherwise using two or more parts. It is a
> > > convenient
> > > > > > > part for the ISA, but since the ISA presents all the other signals,
> > > /IOR,
> > > > > /IOW,
> > > > > > > etc, from which you can derive the required signals in a 16L8
> anyway,
> > > which
> > > > > is
> > > > > > > what most of them used for decoding the addresses, you could make
> > > whatever
> > > > > > > signals you needed.
> > > > > >
> > > > > > Yes exactly direct! There is only decode and direct connection from
> IOW to
> > > > > > input data strobe and IOR to ouput data strobe. Take a look at the
> Asyc
> > > > > > card schematic in the XT tech ref. ALE is not needed for I/O on the
> ISA
> > > > > > bus, only for latching the LA bus (which is above the 64K limit of
> I/O).
> > > > > >
> > > > > >
> > > > > >
> > > > > > > > > >
> > > > > > > > > I checked the actual board, and the PLCC part that I designed in
> to
> > > the
> > > > > > > board I
> > > > > > > > > was thinking about. It turns out the early version used a few
> > > 68-pin
> > > > > PLCC
> > > > > > > > > sockets, and, in fact, there were no 44-pin PLCC's on that
> board.
> > > The
> > > > > part
> > > > > > > in
> > > > > > > > > the PLCC socket, BTW was not a PLCC, but a JEDEC 'C' package.
> > > Though
> > > > > there
> > > > > > > was
> > > > > > > > > paper for the PLCC, the only parts used on the prototype board
> in
> > > that
> > > > > > > > > application were in the JEDEC 'C' package. Fortunately, unlike
> the
> > > > > JEDEC
> > > > > > > 'A'
> > > > > > > > > package, (that leadless single-sided ceramic chip carrier in
> which
> > > > > i80186's
> > > > > > > and
> > > > > > > > > i80286's were commonly used) the 'C' package would easily work
> in a
> > > PLCC
> > > > > > > socket.
> > > > > > > > > A later version, however, did, indeed have the 8250's in the
> PLCC-44
> > > on
> > > > > it.
> > > > > > > >
> > > > > > > > Sure, there are 8250's (and 16450's and 16550's etc etc) in PLCCs,
> > > just
> > > > > > > > not in 1981...
> > > > > > > >
> > > > > > > > > >
> > > > > > > > > I really don't think practical considerations such as cost
> entered
> > > into
> > > > > the
> > > > > > > > > early decision stream in the PC development, once it reached the
> > > point
> > > > > at
> > > > > > > which
> > > > > > > > > upper management was prepared to pull the plug if at least one
> > > milestone
> > > > > > > wasn't
> > > > > > > > > met. The way I heard the story from some of the guys who worked
> at
> > > Boca
> > > > > was
> > > > > > > > > that there wouldn't have been an IBM PC if Intel hadn't
> presented
> > > the
> > > > > guys
> > > > > > > with
> > > > > > > > > a board-level prototype of the '188 (not an application of the
> > > '188).
> > > > > While
> > > > > > > > > it's easy enough to believe that the entire project had
> deteriorated
> > > > > into a
> > > > > > > > > "Chinese fire drill," I can't believe that Intel would have had
> the
> > > > > brains
> > > > > > > to
> > > > > > > > > present a canned solution to them in time to pull the chestnuts
> from
> > > the
> > > > > > > fire.
> > > > > > > > >
> > > > > > > > > Dick
> > > > > > > > >
> > > > > > > > > > > > > ----- Original Message -----
> > > > > > > > > > > > > From: "Peter C. Wallace" <pcw_at_mesanet.com>
> > > > > > > > > > > > > To: <classiccmp_at_classiccmp.org>
> > > > > > > > > > > > > Sent: Friday, December 14, 2001 12:28 PM
> > > > > > > > > > > > > Subject: Re: MITS 2SIO serial chip?
> > > > > > > > > > > > >
> > > > > > > > > > > > >
> > > > > > > > > > > > > > On Fri, 14 Dec 2001, Gene Buckle wrote:
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > NS* did use them as did many others. The worst
> chip
> > > was
> > > > > > > > > > > > > > > > the 8250.
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > Which makes me wonder what possessed IBM to pick it
> for
> > > the
> > > > > PC.
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > g.
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > The same reason they chose active high edge triggered
> > > > > interrupts
> > > > > > > on
> > > > > > > > > the
> > > > > > > > > > > > > > bus (wrong on both counts)
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > The same reason they used 8 bits of an 8255 to read
> the KB
> > > > > shift
> > > > > > > > > register
> > > > > > > > > > > > > > that had a (unused) tri-state
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > The PC = A horrible, amateurishly designed kluge
> > > > > > > > > > > > > >
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > Peter Wallace
> > > > > > > > > > > > > >
> > > > > > > > > > > > > >
> > > > > > > > > > > > >
> > > > > > > > > > > > >
> > > > > > > > > > > >
> > > > > > > > > > > > Peter Wallace
> > > > > > > > > > > > Mesa Electronics
> > > > > > > > > > > >
> > > > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > Peter Wallace
> > > > > > > > > > Mesa Electronics
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > >
> > > > > > > > >
> > > > > > > >
> > > > > > > > Peter Wallace
> > > > > > > > Mesa Electronics
> > > > > > > >
> > > > > > > >
> > > > > > >
> > > > > > >
> > > > > >
> > > > > > Peter Wallace
> > > > > > Mesa Electronics
> > > > > >
> > > > > >
> > > > >
> > > > >
> > > >
> > > > Peter Wallace
> > > > Mesa Electronics
> > > >
> > > >
> > >
> > >
> >
> > Peter Wallace
> > Mesa Electronics
> >
> >
>
>

Peter Wallace
Mesa Electronics
Received on Sun Dec 16 2001 - 11:58:52 GMT