MITS 2SIO serial chip?

From: Peter C. Wallace <pcw_at_mesanet.com>
Date: Sun Dec 16 14:17:39 2001

On Sun, 16 Dec 2001, Ben Franchuk wrote:

> "Peter C. Wallace" wrote:
> >
> > On Sun, 16 Dec 2001, Richard Erlacher wrote:
> >
> > > I disagree that it's a mess. I haven't looked at the requirements for a Z80
> > > peripheral since the early '80's, but I can assure you that I'd dispose of any
> > > 1st year engineering intern who couldn't whip up a suitable PAL or equivalent
> > > MSI/SSI logic to handle the generation of properly timed inputs to the thing in
> > > an hour or less.
> >
> > Sure its trivial to do now but we were talking 1981 when PALS were
> > expensive.
>
> I never heard about pal's until about 1990. In some ways the peripheral
> chips are in a really sorry shape. You have vintage slow I/O (2 MHZ?)
> or PC motherboard chip sets. Nothing in between. On my FPGA I can run
> with a 250 ns memory cycle, but need to stretch it to 625 ns for I/O.

        PALs were certainly available earlier, just expensive,
non-reprogramable, and power hungry. I think we used our first
programmable logic in 1986 (Altera EP900s and EP320s - both low power) for
emulation of some PC motherboard stuff in our low power V40 based embedded
PCs. We never used PALs but have used GALs a lot for simple decoders and
random logic. At about $.50 now they are hard to beat.
        I think I would do most non-common (probably not Ethernet, USB or
video) I/O these days with FPGAs. Its great to be able to change the
function and pinout with just a downloadble config file. A 100K (Well
maybe 15K if you remove Xilinx inflation factor) SpartanII chip is only
$19.00...



>
> --
> Ben Franchuk --- Pre-historic Cpu's --
> www.jetnet.ab.ca/users/bfranchuk/index.html
>

Peter Wallace
Mesa Electronics
Received on Sun Dec 16 2001 - 14:17:39 GMT

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