There's one advantage that you can exploit with the WD parts that the NEC parts
won't support, and that's formatting with interleaving. The NEC parts seem to
be unable to format a diskette with other than strict ordinal sector numbering,
while the WD allows you to number them with any offset you like. The result is
that an interleaved format optimized for one set of system parameters can still
be read by another system without the other system having to be adjusted in any
way. Of course it won't be able to read an entire track in one revolution, but
it will have the ability to read the diskette without introducing a modified
lookup table for sector numbers. I know that doesn't make much difference
nowadays, but back when folks used floppies as their main/only storage medium,
it impacted performance.
Dick
----- Original Message -----
From: "Peter C. Wallace" <pcw_at_mesanet.com>
To: <classiccmp_at_classiccmp.org>
Sent: Monday, December 17, 2001 10:27 AM
Subject: Re: MITS 2SIO serial chip?
> On Sun, 16 Dec 2001, Ben Franchuk wrote:
>
> > ajp166 wrote:
> > >
> > > A newer chip that can still be found is the WD37C65
> > > that will do 125ns easily. Or you could easily find a d765
> > > off an old board or NOS from JDR.
> >
> > The floppy disk chips have arrived in the post friday. I hope to get
> > a chance to pick them monday.I will keep the WD37C65 in mind but
> > "A bird in the hand is worth two in the bush.". I have added wait
> > states internally for I/O.
> >
> > > Allison
> >
> > > I've built enough to enjoy later parts as I'm old enough to want
> > > it done in a lifetime and the older parts meant tons more support
> > > parts and the requisite connections. Of the latter, the fewer the
> > > better for both buildability and reliability.
> >
> > Well I managed to stick my serial uart in the FPGA. One good feature
> > of 'dumb' hardware is that they can be used for bootstrapping the cpu.
> > (Mind you you still need a rather big prom to boot the FPGA but that
> > is another story)
>
>
> I guess you are not using Xilinx, but one thing I've noticed lately is the
> appearance of large, serial flash EEPROMs. We are using one on them in a
> new Xilinx design. The SST part is a 1 Mb chip (128KBytes) 8 pin SOP
> package = $1.35. So instead of Xilinx's $4.40 OTP chip we use a 8 pin PIC
> and the serial EEPROM for a total of $2.29 and get re-programmability...
>
> > --
> > Ben Franchuk --- Pre-historic Cpu's --
> > www.jetnet.ab.ca/users/bfranchuk/index.html
> >
>
> Peter Wallace
> Mesa Electronics
>
>
Received on Mon Dec 17 2001 - 20:04:32 GMT