MITS 2SIO serial chip?

From: Richard Erlacher <edick_at_idcomm.com>
Date: Tue Dec 18 00:06:31 2001

I may have to go out looking for a different one ... that's not the one I was
thinking of when I wrote the item below, as that one spelled it out in terms of
fitting in a specific Xilinx and in a particular Altera part as well as the
associated clock rates. The ones that come in a PLCC-84 are still pretty small,
though. Frankly, I'd prefer a much larger array in a PLCC-44 since one doesn't
need pile of I/O, but the die size makes 'em use a big package to accomodate
whatever sort of lead frame or whatever they use now.

BTW, if you think you can buy that 65C02 from WDC any more, good luck, as I've
never even been able to get them to quote on their fast part. They claim it
runs at 20 MHz, but spec it for 14. Now 14 is pretty fast ...

If you want fast, though, Dallas is sampling their 50MIPs 8051 part (89C420).
They've redesigned the core so it uses one clock tick per instruction cycle, and
most of the instructions that operate internally use only one cycle. The timer
and external memory accesses, however, can be slowed down so (1) you don't have
to use a 16-bit timer as a baud-rate generator, and (2) you can use slow
external devices if you need to. It has promise!

Dick

----- Original Message -----
From: "Ben Franchuk" <bfranchuk_at_jetnet.ab.ca>
To: <classiccmp_at_classiccmp.org>
Sent: Monday, December 17, 2001 4:28 AM
Subject: Re: MITS 2SIO serial chip?


> Richard Erlacher wrote:
>
>
> > The 650x core is apparently known to be about 3300 gates, if you can go by
their
> > putative gate count. However, you can check 'em out for yourself. Google
will
> > turn up several. As you might expect, the Z80 core is quite a bit larger
and
> > runs somewhat slower. I don't think anyone's done the 650x core "right"
yet,
> > because most of the HDL's still are too big.
>
> Lets say 3K gates. Lets also define a small FPGA is one that fits in a
> 84 pin
> PLCC. The FPGA is used just for the CPU - no ram , rom , or I/O devices.
> Looking at free-6502 as a guide. http://www.free-ip.com/6502/
> it is really hard to tell just how many CLB's are used, but are just
> over the
> limit of what fits in small FPGA is what it looks like.
>
> > I remember the trade (~1976-77) mag's telling us that the 6502 was <1/4 the
size
> > of the Z80 though they were in the same technology. The only way I can see
that
> > happening, aside from the vastly reduced internal resources that the 650x
has,
> > is a much slicker design.
> I suspect this is because
>
> 1) All registers but the PC are 8 bit.
> 2) Instructions grouped into fewer internal states per clock.
> I think a z80 instruction could have 17+ states where a
> 6502 used up to 5 states.
>
>
> --
> Ben Franchuk --- Pre-historic Cpu's --
> www.jetnet.ab.ca/users/bfranchuk/index.html
>
>
Received on Tue Dec 18 2001 - 00:06:31 GMT

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