I went back and took a look at the site you cited and found that he'd also put
some specifics with differnt gate array technologies/geometries in the mix. The
numbers are really quite impressive. The 10Kgate version that runs 166 MHz
looks good, but I wonder how close to real that really is.
I'd be really interested in how much smaller the core can be made by useing the
ALU to do the address arithmetic rather than using counters. I'd also be
interested in how big the array gets if you fiddle with the architecture enough
that you have a different address and data space, i.e. a modified Harvard. If
the instruction word were large enough to incoporate the index registers in
every instruction, just no-op them when they're not needed, it would make a
bigger core, but I believe all the instructions would then be single cycle.
That's the two extremes. The latter method would add latency but wouldn't take
a performance hit. It would mean multiple adder/subtractors, though the primary
ALU wouldn't have to be replicated.
Dick
----- Original Message -----
From: "Ben Franchuk" <bfranchuk_at_jetnet.ab.ca>
To: <classiccmp_at_classiccmp.org>
Sent: Monday, December 17, 2001 4:28 AM
Subject: Re: MITS 2SIO serial chip?
> Richard Erlacher wrote:
>
>
> > The 650x core is apparently known to be about 3300 gates, if you can go by
their
> > putative gate count. However, you can check 'em out for yourself. Google
will
> > turn up several. As you might expect, the Z80 core is quite a bit larger
and
> > runs somewhat slower. I don't think anyone's done the 650x core "right"
yet,
> > because most of the HDL's still are too big.
>
> Lets say 3K gates. Lets also define a small FPGA is one that fits in a
> 84 pin
> PLCC. The FPGA is used just for the CPU - no ram , rom , or I/O devices.
> Looking at free-6502 as a guide. http://www.free-ip.com/6502/
> it is really hard to tell just how many CLB's are used, but are just
> over the
> limit of what fits in small FPGA is what it looks like.
>
> > I remember the trade (~1976-77) mag's telling us that the 6502 was <1/4 the
size
> > of the Z80 though they were in the same technology. The only way I can see
that
> > happening, aside from the vastly reduced internal resources that the 650x
has,
> > is a much slicker design.
> I suspect this is because
>
> 1) All registers but the PC are 8 bit.
> 2) Instructions grouped into fewer internal states per clock.
> I think a z80 instruction could have 17+ states where a
> 6502 used up to 5 states.
>
>
> --
> Ben Franchuk --- Pre-historic Cpu's --
> www.jetnet.ab.ca/users/bfranchuk/index.html
>
>
Received on Tue Dec 18 2001 - 00:31:54 GMT