Now I'm really puzzled. After spending the evening playing with my M8650
serial board, and armed with the pinouts this time, I still have an
interrupt problem.
The fault is that the usual operations don't disable the interrupt from the
board. As far as I can see from the PDP-8/E Maintenance Manual, pressing
CLEAR on the panel should enable the interrupts, while issuing a KIE
instruction with AC11 = 0 should disable them. Have I understood this
correctly?
Looks like it does the reverse (I ought to have checked that KIE with
AC11=1 disables it on this board, but I forgot, and it's too cold and late
to go back to the workshop right now. I'll do it tomorrow).
The fault must have been noticed at some time in the past, as someone has
cut the trace to CP1 (INT RQST L output to the bus). If I bridge the cut,
the interrupts remain on all the time, which I suspect is why I can't get
FOCAL to run.
At this point I should mention that my M8650 isn't labelled as a -YA
version, though it has the 19.66MHz crystal and the jumpers to run at 300
baud. It has several very neat modifications made with green wire-wrap
wire, tacked down in the manner of DEC ECOs, but nothing that looks like it
alters the interrupt flipflop operation. The board etch says "M8650 D",
"ASYNCHRONOUS DATA CONTROL", "PCC 3874" and it has "441E" stamped on one of
the magenta handles.
According to the Maintenance Manual, INIT H is buffered and inverted, and
fed to the SET input of the flipflop (which is a 7474). Well, on mine it's
fed to the CLR input. However, according to the MM, the "1" output (which
I'd call the Q output, pin 9) enables interrupts if high, and is available
at CB1, the test point. On mine, pin 8 (not-Q) is connected to CB1 and
used to enable interrupts by driving one side of E33. So far so good, if a
little surprising.
But DATA 11 is fed to the D input as per the MM (buffered and gated with
I/O PAUSE L but not inverted). So KIE with AC11 = 0 clears the flipflop,
which sets not-Q, which enables interrupts. This is not what the
diagnostics expect, and predictably, they fail, halting at the location
that means the interrupt is not turning off when it should. BTW, I assume
that a high level on DATA 11 corresponds to a logic '1'.
Should I just swap the connections to the SET and CLR, and Q and not-Q on
the 7474? Or am I missing something?
--
Pete Peter Turnbull
Network Manager
University of York
Received on Wed Dec 19 2001 - 19:01:48 GMT