Allison wrote:
>
> Bent in that you might want a load to always be some opcode and
> a logic change down stream makes it something different do to gating.
> A PLA or Prom to translate opcodes from a irregular pattern
> of hardware convenience to something regular is handy.
True. The only real trick I used was on reset. This would clear
the instruction register and state counter to zero. I would then
use that to fetch the first instruction. All instructions would
start from state 2. IRQ was jam on the bus the IRQ instruction.
This has changed slightly as of today since I did add a irq input
and made reset now load a octal bootstrap.
> Besides with 48 bits of ucode the address of the next instruction is
> in the ucode and the logic is a really wide prom with a really wide
> latch and a really simple next address select logic (some LS257s).
> No counters or incrementors, The translated opcode from the prom
> was the source of the high order ucode address after a "next
> instuction fetch". Made the ucode very simple though not very
> efficient in terms of bits. Eproms though slow made it cheap with
> bipolar proms as follow up for speed.
I have looked a microcode but not having a PROM burner kept me from
doing anything with it. I found I spent more time writing software
and emulators than thinking about hardware in great detail.
Most of the fixing of bent opcodes have been done before I did the
hardware
but I did make a few changes in the exact opcode order.
> Allison
--
Ben Franchuk --- Pre-historic Cpu's --
www.jetnet.ab.ca/users/bfranchuk/index.html
Received on Wed Dec 19 2001 - 09:13:25 GMT