If you are determined to build a TTL 650x core, you can start with a pair of
74S219's (non-inverting 74S189's) in which to accomodate the registers, with the
obvious exception of the processor status, which requires it be discretely
implemented but shadowed in the register RAM. If you have PCL, PCH, X, Y, A,
SP, a flag shadow and an impending operand (to catch the data bus input), that
will use up half the space. If you then keep the address bus in a couple of
additional locations, so you can get into and out of sequence from the PC, you
will, once you've studied the MOS Technology hardware reference, easily see how
the device works. Keep in mind that by using two tristate buses you can route
data from the tristate RAM to the ALU inputs quite easily. Also, if you
consider that the clock phases easily support using the ALU to do the address
arithmetic as well as operand arithmetic, you'll see why the chip was so small.
If you use tristate multiplexers to accomplish the various shifts and rotates,
and use a set of XORs to make an adder-subtractor from a pair of '283's, you'll
have most of the workings. The rest is a pair of one-hot sequencers to
concatenate the logic paths through the ALU on each clock phase.
have fun!
Dick
----- Original Message -----
From: "ajp166" <ajp166_at_bellatlantic.net>
To: <classiccmp_at_classiccmp.org>
Sent: Sunday, May 06, 2001 10:46 AM
Subject: Re: How many transistors in the 6502 processor?
> From: Brian Chase <bdc_at_world.std.com>
>
>
> >Nice, now if I could only get enough info to implement one in TTL. :-)
> >Silly, yes, but it would be a fun project.
>
>
> Well you know the timing, instruction set, internal organization
> and register set... what else do you need? Granted VHDL would
> be nice but the internal circuit schmatics as built are anything
> but TTL.
>
> The biggest difference from the mos version going ttl would
> likely result in is a static register cells instead of dynamic
> making the result fully stopable.
>
> Allison
>
>
Received on Sun May 06 2001 - 12:06:03 BST