Ah yes but, the CMOS ram would cause one problem for the
design... Common IO. The 74189/289 had seperate IO unless
I've suffered a major brain cramp.
Allison
-----Original Message-----
From: Richard Erlacher <edick_at_idcomm.com>
To: classiccmp_at_classiccmp.org <classiccmp_at_classiccmp.org>
Date: Friday, November 02, 2001 11:28 AM
Subject: Re: classiccmp-digest V1 #761
>The '289's are inverting, though tristate, just like the '189's. TI made a
'219
>which was a noninverting tristate version of this same sort and pinout.
ISTR
>that there was yet another part, albeit not of the normal 74xxx sort, that
was a
>non-inverting version as well, but I can't, for the life of me, rememberit
>(senior moment). These days, it's both cheaper and easier (faster, too) to
use
>a CMOS ram of considerably larger size.
>
>Dick
>
>----- Original Message -----
>From: "Ben Franchuk" <bfranchuk_at_jetnet.ab.ca>
>To: <classiccmp_at_classiccmp.org>
>Sent: Thursday, November 01, 2001 5:17 PM
>Subject: Re: classiccmp-digest V1 #761
>
>
>> ajp166 wrote:
>> >
>> > Those parts were never cheap!
>> >
>> > You can also use 74289s for the '189s. The '382s are an improved
version
>> > of the '182. A note, if you can tolerate a slower ALU you can omit the
>> > '382s
>> > and just use ripple carry.
>>
>> If the 74289's are the non inverting 16x4 rams I would use them. I plan
>> to use 74ls382's (the ripple carry alu's).
>>
>> > A sub for 74189s is some of the byte wide cache rams from an old
386/486
>> > PC as the faster ones were faster than the TTL 74189! You dont have to
use
>> > the full space of the cache ram though having it would make afor an
>interesting
>> > register array.
>>
>> Can't do that for three reasons
>> 1) I am use a 16 x 12 ram ( 3 chips ) on two boards for a 8 x 24
>> register array.
>> 2) I am using the 486 cache chips as main memory in my FPGA prototype
>> 32k x 12 bits.:)
>> 3) This was a TTL design on paper of what a computer designed in the
>> early 1980's
>> could have been like. That rules out 2901 bit slices.
>>
>> > Allison
>> As it stands today I have a FPGA ( pat pat pat ) that is configured to
>> have a similar
>> layout as the ttl design and this lets me play around with the
>> configuration. Mind you a
>> larger TTL CPU with lights and switches is more impressive. If you like
>> lights
>> and switches here is a neat link http://www.angelfire.com/scifi/B205/
>> 'to the Bat Cave'
>>
>> Ben Franchuk.
>> --
>> Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
>> "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
>> Now with schematics.
>>
>>
>
Received on Fri Nov 02 2001 - 10:40:50 GMT