CPU design at the gate level

From: Richard Erlacher <edick_at_idcomm.com>
Date: Sat Nov 3 12:48:53 2001

see below, plz.

Dick

----- Original Message -----
From: "Chuck McManis" <cmcmanis_at_mcmanis.com>
To: <classiccmp_at_classiccmp.org>
Sent: Friday, November 02, 2001 9:44 PM
Subject: Re: CPU design at the gate level


>
> > > Nowadays, you're
> > > required to use a 1000+ pin BGA package to get the quantity of logic
> > that you'd
> > > like in a 44-pin PLCC.
>
> The above statement is completely untrue. You can get 10 - 100x the "ttl"
> equivalent logic in a 44 pin PLCC. Check out the XC9572 some time,
> depending on your logic you can replace a whole bunch of TTL and they are
> $5.53 each from Digikey, quantity 1. Or go to 84 pin PLCC, still allows you
> to do through hole work for $7.00 and get 50% more gates.
>
I think you've misinterpreted what I meant with "what you'd like." I once
lamented that I couldn't get a 100K gates in an 8-pin package, an obvious
impossiblility because of the die size, because the presence of the extra pins
made me feel the device contents could be too easily compromised. I'm quite
familiar with the XC9572. and it is available in a 44-pin part. However, it's
not an FPGA, and the fact that it isn't makes a big difference in how much of
the purported gate count you can actually use. With cpld's like the XC9572, you
can use pretty much all the available logic without a hitch, though it still
won't approach their (XILINX's) gate count.

Their marketing guys have decided at some point to take the most extreme
interpretation of "gate-count" i.e. a count based on the definition of a gate as
a two-input NAND, and they count gates based on the notion that a three-input
nand requires two NANDs plus one as an inverter, so they count it as three
gates. On that basis the usual 6 gates required for a 'D' register become quite
a few more, and, of course, a 32-bit LUT has 32 of them, plus a bunch more to
decode the LUT, right? That's what you consume to build just one functional
gate, though, isn't it? My point was and is that the "gate count" has amost no
direct correspondence to what you can put into a device. After a while you
learn what each device can do for you and so long as you don't try to switch
from one family to another, you can almost rely on what you learn.
>
> > If you're really lucky with the fit, the device will
> > > allow you to use 10% of the gate count the marketing guys said you're
> > paying
> > > for.
>
> If you're a really lousy logic designer you can create crap anywhere, no
> need to go the FPGA route.
>
I recently went a round with the Altera folks, only to find that their current
software wouldn't, no matter how hard you tried, produce a fuse map for one of
their "classic" devices that the software that was popular with those devices
(APLUS+) would readily yield. The MaxPlus-2 software requires exactly twice the
resources that the old APLUS+ required to create the same construct. Try
generating a COLF (combinatorial output with latched feedback) macrocell
architecture in the current generation of Altera, or, for that matter, Xilinx,
software and see how much of the device resources it requires. Try building the
logical equivalent of a 74BCT2424 using the current generation software and see
what their devices leave over. Now try to fit that into a device that has the
same pin count.
>
> [the price comments were still more crap]
>
You wouldn't say that if you'd ever had to deal with the actual costs yourself.
>
If you try to use a couple of their higher-gate-count parts you'll find they're
not readily available in packages you can use for prototyping without first
mounting the parts on an adapter PCB. The BGA's are notoriously difficult to
attach to such adapters and, since that requires lots of effort, it's costly.
If you'd ever tried this, you'd know what I mean. The parts folks use in
production, e.g. the pqfp and tqfp packages are impossible to use in prototypes
because of their fragility. Getting around that means a large cost. If you're
building a revision of an established product and have a deep-pocketed employer,
you can get by with this, but if you're building a proof of concept, which is
what these devices should do best, being readily reprogrammable, the mechanical
constraints and costs get in the way.
>
> >Don't forget the $500 minimum order per line item. I suspect you need
> >all the 1000+ pins since only 50% of the pins are usable -- the power,
> >ground and configuration pins take up a lot of space.
>
If you look at some of the considerably smaller (in putative gate count) devices
in PGA packages you will see that Avnet, among others lists these parts at
ridiculous prices, probably because of the limited consumption of that package.
>
> If you use something like the XV1000 (1 MILLION equivalent gates, then yes
> the chip will cost you $1700 and you can design in a complete PDP-11/70,
> GT-44 subsystem, RL/RK/RX controllers, SDRAM memory controller, front panel
> for blinken lights, full floating point, CIS and EIS instruction sets and a
> programmable microstore with about half the damn chip left over.
>
I don't think you actually believe that, though it seems you do believe some of
what their marketing folks tell you. However, the fact you have half the chip
left over is because you can't route to the unused resources and still maintain
timing constraints.
>
> Sheesh, don't dis 'em if you don't know anything about them.
>
They're useable devices, to wit, you can't do anything these days without 'em,
but they're falsely advertised, not convenient to use over their full range, and
VERY costly to use. I have no respect for their marketing claims, but mainly
have problems with their packaging because it's very difficult and costly to
apply to my particular niche.
>
> --Chuck
>
>
Received on Sat Nov 03 2001 - 12:48:53 GMT