CPU design at the gate level

From: Allison <ajp166_at_bellatlantic.net>
Date: Tue Nov 6 07:35:36 2001

Yes but I was working on the presumption of xN=8
and for every permutation of 8bit A and 8bit B.

Allison
-----Original Message-----
From: Greg Ewing <greg_at_cosc.canterbury.ac.nz>
To: classiccmp_at_classiccmp.org <classiccmp_at_classiccmp.org>
Date: Monday, November 05, 2001 11:41 PM
Subject: Re: CPU design at the gate level


>ajp166 <ajp166_at_bellatlantic.net>:
>
>> Whats
>> problemtic is that the ALU must do about 8-16 different operations
>> so that would be at least a 512kN part or larger.
>
>Not that big, surely? 4 A inputs, 4 B inputs, carry input,
>4 function select inputs comes to 13 inputs, so 8KxN
>should be enough.
>
>Greg Ewing, Computer Science Dept, +--------------------------------------+
>University of Canterbury, | A citizen of NewZealandCorp, a |
>Christchurch, New Zealand | wholly-owned subsidiary of USA Inc. |
>greg_at_cosc.canterbury.ac.nz +--------------------------------------+
>
Received on Tue Nov 06 2001 - 07:35:36 GMT