Core Memory Interfacing?

From: Allison <ajp166_at_bellatlantic.net>
Date: Wed Apr 3 12:31:00 2002

Not that many trasistors more like 128 diodes.
You would need to know:

    1-The switching current for the core:
    2-the half select current(related to #1):
    3-Time to switch
    4-is it a 2d or 3d array(word or bit frame)
    5-single sense/inhibit or serperate sense and inhibit lines.

Words are driven by the same drivers as an individual bit so
that saves parts. Generally there is an array of multiplexed
devices to drive the array, for a 64x64 that would likely mean
only 128 driver devices (best done as integrated stuff like
TI 754xx parts) and a lot of steering diodes.
You will need a sense amp per bit and an inhibit driver per bit.
Most core systems use a delay line to get the timing as the
cycle is RMW (read/modify or rewrite) as core is destructive
read out (generally) so you have to write the data back. The
time you sense the bit change is tied to the core used and
varies some with temperature and current. Also the sense
amp must discriminate from noise and a valid pulse related
to a bit change.

Oh, it will be slow. Most core system were over .5us{500nS}
Tacc and Tcy are typically 1.0-1.6us{1000-1600nS} .

It's a rewarding task but non-trivial nor small. FYI: you need
a heafty low noise multiple voltage power supply to run it.

Me, I'm looking at a 16k semiconductor memory replacement
for a PDP-8f that is simple. This would be a resource to those
that have found an -8 without enough core or to replace bad
core. This is of course a IMCFT project.

Allison
{IMCFT >>> In My Copious Free Time}

-----Original Message-----
From: Bill Richman <bill_at_timeguy.com>
To: classiccmp_at_classiccmp.org <classiccmp_at_classiccmp.org>
Date: Wednesday, April 03, 2002 12:58 PM
Subject: Core Memory Interfacing?


>Right off, let me say that I know next to nothing about the realities of
>using core memory. I only know that it looks like pretty cool stuff to
>play with. Would I be completely off my tree to try to build a core
>memory interface from scratch, assuming I had a pre-strung core frame with
>all the cores and wires intact? When I say "interface", I mean basically
>something that will let me talk to the core from a PC or from my
>recently-completed Mark-8 using TTL or CMOS levels. If I have a 64x64
>frame, would I just need something on the order of 256 driver transistors
>(one to drive each of the X and Y wires in either direction) plus some
>kind of op-amp or comparator circuit to monitor the sense wire (is there
>just one of these per frame?) and determine whether or not a bit has
>flipped during a read pulse? Or are there all sorts of ghosts and goblins
>lurking in core memory that I don't want to confront?
>
>
>
>
Received on Wed Apr 03 2002 - 12:31:00 BST