TTL computing

From: Richard Erlacher <>
Date: Tue Apr 9 23:44:00 2002

see below, plz.


----- Original Message -----
From: "Ben Franchuk" <>
To: <>
Sent: Tuesday, April 09, 2002 9:38 PM
Subject: Re: TTL computing

> Tony Duell wrote:
> > For experimental and educational projects I much prefer TTL (including,
> > of course the CMOS versions of the TTL chips, like 74HCxxx parts). It's
> > easier to prototype with, easier to test (you can clip the 'scope or
> > logic analyser wherever you like), and easier to see what's really going
> > on. It's quicker to make small changes to the circuit as well (on an FPGA
> > design I did about 5 years ago, a full compile of the main chip took
> > overnigh (OK, PCs have got faster since then, but FPGAs have also got
> > larger!)). That meant every small change took a day to test. A soldering
> > iron and/or wire-wrap tool is a lot faster for changing a few connections
> > :-) You also aren't tied to a proprietry program running on some
> > computer/OS that I don't have...
> Until I got over 95% of logic filled in my Altera FPGA, most compiles
> were under 15 minutes.( BTW -- Since I have 100% of the FPGA used it is
> time to stop upgrading the design :)). I live in the middle of (looks
> around) snow thus getting stuff mail order is the only way to get parts
> often from the USA but some even from Australia.
I've seen/heard of very few FPGA's getting much past 30% utilization, based on
the gate counts proffered by the marketing droids. Remember that they count a
3-input gate as 3 2-input gates and a flipflop as 14 rather than 6 gates.
Therefore, if you use a 32-bit LUT, the marketing people take credit for 32 *
14 gates, plus a huge multiplexing tree counted as though it were built from a
sea of 2 input gates. Just the same, regardless of how you count 'em, the
utilization under most circumstances remains well under half the available

Some of the configurations that were easily produced using the old Altera
APLUS+ software in a 24 macrocell Classic (EP910) can't be implemented in a
Classic EP1810 (twice as large, twice as many macrocells) with the
current-generation software because some of the constructs (bidirectional
macrocells, latches, etc.) of which the old software was capable don't exist
in the new software. It seem strange ...

If you get well above that level of utilization, you must be VERY good!
> > Please don't attempt to convince me that FPGAs make more sense for
> > production. I don't need convincing of that...
I'm not sure they're particularly appropriate for production unless the
circuits in which they're used are very large indeed, since it's tempting to
put ALL the logic in one of them, thereby making it child's play for
counterfeiters or your competitors to replicate your work.
> TTL is still better for production. (grin).
> > I wouldn't call those SSI parts.
> Ok SSI and MSI parts. Compared to millions of transistors in a cpu, all
> TTL parts are small. BTW altera has a fairly nice macro library for
> their FPGA's.
> > Why? The '181 has many more operations, some of them useful....
> I want A+~B,~A+B,A+B,A^B,A|B,A*B alu functions. The 181 can't give me
> that.
> > Sure... I guess 74x170s are really hard to find now :-(.. All these
> > wonderful chips I grew up using are discontinued :-(
Well, I just received some '670's. They're tri-state where the '170's are OC.
Aside from that ...

This particular application is an enhanced parallel port monitor, and the
two-port register set is perfect for the application. The pair receives data
in bytes and coughs it up in nybbles for display. In fact, I have a problem
with the range of SRAMs that are avaisable today, as they're too deep, making
them slow, and too narrow, meaning one has to use too many. I need 8 words of
256Kbits more often than I need 256K words of 8 bits. Since FPGA's are just
SRAMs with feedback, it's obvious that shallow SRAMs of sufficient speed (<250
ps Taac) can be fabricated, but they just don't find their way into useable
> More like a 74xx00. The Tiny chips are sure popular today, who would of
> thought single gate chips would sell.

It has to do with layout. If you have 4 NAND gates in a package, costing what
4 gates would, you'd be tempted to share the gates among different circuits.
If those circuits are more than 10mm apart, the routing uses up too much real
estate, so a single gate is reasonable.
Received on Tue Apr 09 2002 - 23:44:00 BST

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