> I've seen/heard of very few FPGA's getting much past 30% utilization, based on
> the gate counts proffered by the marketing droids. Remember that they count a
> 3-input gate as 3 2-input gates and a flipflop as 14 rather than 6 gates.
> Therefore, if you use a 32-bit LUT, the marketing people take credit for 32 *
> 14 gates, plus a huge multiplexing tree counted as though it were built from a
> sea of 2 input gates. Just the same, regardless of how you count 'em, the
> utilization under most circumstances remains well under half the available
> resources.
Well regardless of how you count them, the chip has no free macro cells
left, and routing is very full with only a few free I/O pins.
> Some of the configurations that were easily produced using the old Altera
> APLUS+ software in a 24 macrocell Classic (EP910) can't be implemented in a
> Classic EP1810 (twice as large, twice as many macrocells) with the
> current-generation software because some of the constructs (bidirectional
> macrocells, latches, etc.) of which the old software was capable don't exist
> in the new software. It seem strange ...
Lets not forget everything in BGA pin format too. That is the other
reason why it so full, I can't move to a larger FPGA and still stay in a
84 pin PLCC package.
> If you get well above that level of utilization, you must be VERY good!
Nope just luck and trial and error ... does feature X fit ... nope , how
about Y ... then feature Z..
> This particular application is an enhanced parallel port monitor, and the
> two-port register set is perfect for the application. The pair receives data
> in bytes and coughs it up in nybbles for display. In fact, I have a problem
> with the range of SRAMs that are avaisable today, as they're too deep, making
> them slow, and too narrow, meaning one has to use too many. I need 8 words of
> 256Kbits more often than I need 256K words of 8 bits. Since FPGA's are just
> SRAMs with feedback, it's obvious that shallow SRAMs of sufficient speed (<250
> ps Taac) can be fabricated, but they just don't find their way into useable
> packages.
$%#! packages all 8 bits wide, how the **** do you find 4 bit wide
memory for all the 12 bit cpu's out there.
> It has to do with layout. If you have 4 NAND gates in a package, costing what
> 4 gates would, you'd be tempted to share the gates among different circuits.
> If those circuits are more than 10mm apart, the routing uses up too much real
> estate, so a single gate is reasonable.
Other than inverting a chip select, I really can't see why such glue is
needed.
--
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html
Received on Wed Apr 10 2002 - 00:23:36 BST