TTL computing

From: Peter C. Wallace <pcw_at_mesanet.com>
Date: Wed Apr 10 12:39:19 2002

On Wed, 10 Apr 2002, Heinz Wolter wrote:

> any details on your Sweet16 design?
> Which fpga/cpld have you managed to
> squeeze it into?
>
> cheers
> heinz

        I guess this is pretty much off topic but doing a simple CPU in a FPGA
is kind of like going back in processor history, I'm having lots of fun
looking through 1960's computer architecture books looking for ideas...

        The Sweet16 a simple pipelined 16 bit (data and instruction)
accumulator oriented processor for our FPGA based servo motor control cards,
using Xilinx Spartan II chips. In some ways the instruction set is a little
like the PDP8 but with 16 basic instructions instead of 8, and indexed memory
access via index registers(3) instead of via special memory locations.


instructions:

                        Addressing modes
OPR Operate A/I (operate include load immediate, rotates etc)
JMP D/*r
JMPNZ D/*r
JMPZ D/*r
JMPNC D/*r
JMPC D/*r
JSR D
AND D/*x/*y/*z/*x+/*y+/*z+
OR D/*x/*y/*z/*x+/*y+/*z+
XOR D/*x/*y/*z/*x+/*y+/*z+
ADD D/*x/*y/*z/*x+/*y+/*z+
ADDC D/*x/*y/*z/*x+/*y+/*z+
SUB D/*x/*y/*z/*x+/*y+/*z+
SUBB D/*x/*y/*z/*x+/*y+/*z+
LDA D/*x/*y/*z/*x+/*y+/*z+
STA D/*x/*y/*z/*x+/*y+/*z+

        We used the KCPSM (Ken Chapmans excellent little 8 bit RISC CPU)
before but found out that for multi axis motion control we ended up doing a
lot of

ld r1,xxx
ld r2,yyy
add r1,r2
st r2,yyy


The lesson here being that for tasks that have a large data set, registers are
not much use unless you can re-use them immediately, or have 100s of them(see
below). We have a large number of 32 bit variables and constants. so even if
we had a 16 or so 16 bit registers it wouldn't help much, heck, for what we
are doing there aren't even any loops to speak of...

so with an accumulator architecture

this becomes

lda yyy
add xxx
sta yyy

a little more efficient...

        We also wanted a little more speed to be able to do 8 Axis with a >12
KHz sample rate, so we did a 16 bit design that is pipelined so that it can do
1 instruction per clock (with 2 delay slots after conditional jumps and some
2 clock data hazards)


        A crazy idea I had is to have a writeback bit in the memory reference
instructions of a single address machine (the option of a free STA) my example
on a single address machine would go from 3 to 2 instructions:

lda xxx
add,sta yyy


This is basically free because the blockram in the SpartanII is dual ported

If you want the (somewhat naive) VHDL for the Sweet16, I can email it to
you...


>
> "Peter C. Wallace" <pcw_at_mesanet.com> wrote:
>
> > Actually It's not that bad, recompiling my Sweet16 16 bit CPU takes
> > only about 5 minutes using Xilinx tools (on a fast machine though) The
> tools
> > are available free (webpack). The tools do require Windows, but some
> people
> > have reported success using them under WINE on Linux.
>
>
>

Peter Wallace
Received on Wed Apr 10 2002 - 12:39:19 BST