TTL computing

From: Richard Erlacher <>
Date: Wed Apr 10 12:56:40 2002

see below, plz.


----- Original Message -----
From: "Ben Franchuk" <>
To: <>
Sent: Wednesday, April 10, 2002 9:50 AM
Subject: Re: TTL computing

> "Peter C. Wallace" wrote:
> > Actually It's not that bad, recompiling my Sweet16 16 bit CPU
> > only about 5 minutes using Xilinx tools (on a fast machine though) The
> > are available free (webpack). The tools do require Windows, but some
> > have reported success using them under WINE on Linux.
> Details ... I want to know that ISA. :)
> > Nah, there 100's of them in a $19.00 FPGA...
> Nope Just the X brand of FPGA's. I use the A-brand of FPGA's because at
> the time the 10K10 was the only chip that looked BIG in a low cost FPGA
> kit. ( 2 years ago ). They don't have 16 bit dual port memory like X.
They (brand A) don't have the internal tristate resources either. That means
lotsa MUXes to do what a tristate bus would do, and you know what that does to
resource allocation, routing, and timing.
> I may do a CPU design with PLD's rather than one large FPGA as they have
> two advantages 1) They can be programed externaly and stay that way 2)
> they are about the right submodule size --- uart , floppy disk, bit
> slice for playing around with custom logic.
If you look at the Cypress CPLD's, I think you'll find them large enough to
put the whole she-bang, i.e. CPU, FDC, HDC, I/O, RAM, ROM on one device. The
advantage is that with a CPLD theres no doubt at all about what the timing
will be and whether you can use this register or that, since you can ALWAYS
use 100% of the resources. What I find hard to fathom is that with the
FPGA's, you pay for 16Mgates and can use barely 4M of them, and that only if
you're fortunate enough to be able to route to every LUT.
> --
> Ben Franchuk - Dawn * 12/24 bit cpu *
Received on Wed Apr 10 2002 - 12:56:40 BST

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