Richard Erlacher wrote:
> I'm not sure I buy that ... the carry is a single product term, isn't it?
> That's why fast carry terms work faster than their respective sum terms, in
> physical adders. In lookup tables, it doesn't matter.
Nope it is recursive.
C[n] = (A[n] and B[n]) | C[n-1] and (A[n] xor B[b])
> FPGA makers take lots of trouble to ensure that you have fast carry logic
> available.
Not all of them. Most people think Xlinix is the only FPGA maker.
> That works OK if you're building stuff you know will work the way you predict
> because people have built it for years. If you're trying something new, the
> simulator saves lots of money for hardware you may not ever need.
Not all the time. On the FPGA design I have done needed a RS232 uart.I
built the uart but got the sense of the start bit wrong. All the
software testing would not have found this problem. That is not to say
simulators are not useful, I have just found gate level simulations to
be less useful than hardware testing of the device. One thing that is
very useful is a cross assembler and instruction simulator to get the
'feel' of the architecture just right.
> Testing, in fact, exhaustive testing of every feature in every combination and
> range of permutation you can generate is essential. Nothing should ever be
> comitted to hardware until you're sure of how it works under all conditions.
How do you test hardware if you don't build it?
> Yes, and it's so slow, even a cheap oscilloscope can show you real features of
> what's going on. Unfortunately, they don't make oscilloscopes fast enough any
> more, that you can see what's really going on with an event that happens every
> ten seconds or so and has a 130 ps duration.
What scope? I got a $10 multi-meter and leds and switches. Most of my
logic debugging now is the DUH! type of logic bugs.
The simulator can show you where
> to look, however, if you've got a simulator and appropriate models for the
> TTL. You can't stick your 'scope or LA into the programmable logic, so you
> have to do what you can with the simulator.
The other reason is that using a simulator or HDL for design is that i
have to wade thru all the stuff to do some thing simple.
Also playing around with CPLD's the most I can reduce logic down to is
by 1/3 as most ttl used is MSI.
--
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html
Received on Wed Apr 17 2002 - 00:27:01 BST