On Thu, 15 Aug 2002, Ben Franchuk wrote:
> Peter C. Wallace wrote:
>
> > Our firmware is in assembler, the problem is what version of the
> > assembler, since the CPU may change daily... I do pretty well know the opcodes
> > in hex, ( I deliberately made add = AXXXXh, NOP = 0000h) but whenever I change
> > some bit field definition I forget what the machine code looks like anymore...
>
> Hex what is that. OCTAL is the way to go!
> Ban all 8/16/32/64 bit computers ... Bring back 18/36 and 12/24 cpu's!
> A 18 bit PDP-11 would have been so nice!
>
> > My CPU sort of looks like a pipelined 16 bit PIC so architecture wise
> > it dates from an on-topic time...
> >
> I designing a 12/24 bit cpu that is in the 1980-1985 time frame.
> http://www.jetnet.ab.ca/users/bfranchuk/index.html
>
> We have a lot of 16 bit cpu's so what is the advantage of your design over
> others. 64K byte memory is the minumum useful memory for a computer. 12K
> operating system, 48K data & program space. While that is two chips nowdays
> for 32KB ram / 32 rom memory even for a controler that is limited memory.
>
Well actually we considered a 24 bit design, Heck I like 24 bit
designs, and since our application is motor control, 24 bits is fine for
most position ranges, but for a simple pipelined (1 clock per inst) RISCy
Harvard architecture processor you get into this tradeoff that depends on how
much of your code does math where the 24 bits is an advantage and how much is
simple logic or I/O where 8 bits would be preferable. !6 bits seems about the
right compromise for us.
BTW we only have 1K or 2K of program and RAM space (all BlockRAM on
chip ) If we had to use external RAM we would do things another way. As it is
we have a 4 axis servo motion controller with quadrature inputs, PWM outputs,
32 bit motion parameters, 64 bit accell and velocity DDAs, PID+Accel and Vel
feed forward control loop, position and programable external event
breakpoints, parabolic and cubic rampup-slew-rampdown profiles and s sample
rate (all 4 axis in motion) of about 35 usec, not bad for a $19.55 FPGA
chip...
>
>
>
Peter Wallace
Received on Thu Aug 15 2002 - 13:33:01 BST