chip pinout help

From: Peter C. Wallace <pcw_at_mesanet.com>
Date: Fri Aug 23 10:18:01 2002

On Thu, 22 Aug 2002, Jim Battle wrote:

> At 01:33 PM 8/22/02 -0700, you wrote:
> > >From: "Eric Smith" <eric_at_brouhaha.com>
> > >
> > >> Hmm, but then how is translation done on the inputs to the ROM? It is
> > >> a TTL device feeding the address, so the 0-5v swing (0.5v to 4+v)
> > >> swing would appear to be an input swing of +15 to +20.
> > >
> > >No translation required. PMOS thresholds are within a few volts of the
> > >positive rail.
> > >
> > >
> > >
> > >
> >
> >Hi
> > The only issue with PMOS is on the outputs. They
> >may not pull down as hard as a TTL input pulls up.
> >This is generally fixed with a pull down resistor
> >and/or a diode to limit the negative travel. Some
> >TTL can tolerate some negative on the input, most
> >CMOS can't ( I think the 4049 can though ).
> >Dwight
>
> Ah, master, you are precisely right. The circuit pulls down with 6.8K to
> the -V. Still, I'm surprised that 74xx inputs will take the output (I'm
> assuming that the PMOS outputs ran rail to rail). There is a clamp diode
> on the input of 74xx devices, but with a >10V difference, I'd expect either
> the driver or receiving clamp diode to complain.

        It is also possible the the PMOS outputs are open drain so the current
from the pulldown resistor is all that the clamp-diode sees...


>
> This is all just for my education -- the board does exactly that and I've
> learned that empirical proof takes priority over my speculations.
>
> -----
> Jim Battle == frustum_at_pacbell.net
>
>

Peter Wallace
Received on Fri Aug 23 2002 - 10:18:01 BST