Apple II hi-res and DRAM refresh (was RE: TRS-80 Model III)

From: Ethan Dicks <erd_6502_at_yahoo.com>
Date: Wed Aug 28 11:40:00 2002

--- Roger Merchberger <zmerch_at_30below.com> wrote:
> Every machine has it's pros & cons... the video memory mapping that
> seemed to defy logic on the Apple ][s is one of the main reasons why
> I never stuck with them...

With my early experience having come from the Commodore world, I admit
that the hi-res mapping on the Apple ][ struck me as odd, too; but when
I programming professionally on it, our graphics guru whipped up a fast
and simple row->address lookup routine and we didn't have to worry about
it from an application standpoint.

The "logic" is that the video refresh circuit doubles as a DRAM refresh
counter. By decoupling the sequential nature of the CPU's view of the
hi-res page and the video output circuit's view of the same memory,
the timing lines up and results in a simpler refresh circuit (i.e., you
don't have to refresh every byte in a DRAM chip, just every row, every
so often; the mapping is driven by the bit geometry of the 4116 DRAM
and how many columns there are per row). I forget how many chips Woz
saved, but I think it was between 1 and 4.

-ethan


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Received on Wed Aug 28 2002 - 11:40:00 BST

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