On Thu, 26 Dec 2002, David Gesswein wrote:
> >(warning: this server is a bit slow)
> >
> Seems fine from here :-). It's a mighty 486-133 (and meets the 10 year rule)
> with a 384k DSL. Most of the documents have a link to a copy mirrired on
> highgate which has better connectivity. I assume it was the speed of
> downloading the documents you were commenting on.
Yes, it took a while for the page to come up after I clicked on the link.
But anyway, thanks very much for providing the scan. Without it I would
be sunk!
> It appears to be driven by a TTL Logic. Page 10-3 shows the output connector
> which data lines go to the control card pg 10-20 and the returns go to the
> DC return (power supply ground). From page 5-6 which you got the output
> diagram from it says that twisted pair cable was recommended with the
> returns terminated close as possible to the data receivers. Running
The cable I used was a 50-pin SCSI, and the lines inside were all twisted
pair, so that much is good. I of course used one pair for each signal pin
and its return.
> the grounds with the data lines in the twisted pair like that gave a little
> more noise immunity. The control card parts list (PG 12-31) seems to have a
> couple versions, normal TTL (7404), open collector outputs (7416) with pullups
> or open collector with inverted data (7417).
So I guess I should open my reader up and find out which version it used
in order to determine how to wire up my connector to the 6522?
> I wouldn't bother with the optoisolators and I don't think the PDP-8 card
> did either. Anybody have a spare M843 CR8E card reader control
> or schematics for it? Polling from an Apple ][ should be slow enough that
> it won't see the glitches that are likely to happen on transisions of the
> index mark signal. I frequently will read strobe signals like that until
> I get the same value twice then act on it.
Jim Willing also warned of the glitches. He said it was so noisy that it
was a challenge to build a proper receiver.
At any rate, the way I understand it, I wait for the IM (Index Mark)
signal from the reader to go high which indicates a column has been read.
Shouldn't the character data be stable at that point? What am I missing?
Here's the process I gleaned from the docs:
1. Put the PC (Pick Command) pin high for 1us*.
2. The BSY (Busy) indicator pin will go high when the leading edge of the
card is detected (and will go low when the card clears the reader track).
3. There will be an IM (Index Mark) every time a column has been read, and
so the data for each column should then be available on the data signal
pins (D1-D9,D0,D11,D12).
* For card-at-a-time mode, the PC pin should be pulsed for 1us to draw the
next card from the input hopper. For continuous mode, PC should be kept
high.
Sellam Ismail Vintage Computer Festival
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Received on Thu Dec 26 2002 - 16:23:00 GMT