M200 interfacing

From: pete_at_dunnington.u-net.com <(pete_at_dunnington.u-net.com)>
Date: Mon Dec 30 07:44:00 2002

On Dec 28, 19:53, Sellam Ismail wrote:

> The next step is to wire in the data signals and start to read data. The
> VIA gives me two 16-bit ports and an additional 4-bit port.

That's an odd VIA. You mean a single 6522, right? It has two
bidirectional 8-bit ports, each of which has 2 associated handshake lines.
 Each of the bidirection lines can be set to be an input or an output, so
it might seem like you have 16 possible inputs and 16 possible outputs --
but you only have 16 connections (plus 4 handshake).

> Anyway, I'm in the process of figuring it out. Everything on the card is
> accessed through it's I/O addresses, being C080 + (slot * 16). So I have
> it in slot 4 which makes all it's I/O available at C0C0-C0CF. I've found
> the timer locations and some 16-bit registers.

The only 16-bit parts of a 6522 are the timers. Timer 1 is a 16-bit
counter accessed as two adjacent 8-bit bytes, and two 8-bit latches (used
to reload it when it counts down to zero). Timer 2 is a 16-bit counter
accessed as two adjacent 8-bit bytes, without latches (so useful only for
counting pulses, or as a one-shot interval timer).

> I also found by accident a
> timer that generates a RESET interrupt when it elapses--at least that's
> the theory I'm going under since the Apple reset itself after I was
> playing with the registers. I also believe I remember there being this
> feature on the 6522, but I haven't had a chance to read that part of the
> docs yet.

A 6522 doesn't have any pin that would normally go to the RESET line, but
it does have an interrupt output. If you set something in register 14 (the
Interrupt Enable Register) and a timer timed out, or you created a
transition on one of the handshake lines, the 6522 would generate an
interrupt. The interrupts on a standard Apple ][, ][+ or //e aren't used
-- it does all normal operations by polling, which is why it's so slow for
some things -- and an interrupt causes the processor to jump to a location
in the ROM. Just where depends on the ROM, but in an original Monitor ROM
or an Autostart ROM, it ends up either going directly to the same routine
as BRK does (which will perform the equivalent of a soft reset) or jumps
through a vector which you're supposed to set up first. If you've not
preset that, I think it ends up in the BRK routine (it certainly does in an
Autostart ROM).

> One thing I'd like to investigate after I'm done with this is to see if
> there are enough inputs on the Apple itself to forgo the necessity of the
> 6522. The Game I/O port has 7 inputs, if you count the 4 joystick inputs
> that can be used as simple TTL inputs, plus the 3 push-button inputs.
 The
> other inputs would be the keyboard. It has 10 Y-inputs and 6 X-inputs,
> plus SHIFT and CONTROL.

Er, not exactly. As Tony pointed out, the keyboard includes a decoder
(called a ROM in the manual), and the key matrix is decoded by scanning.
 Either the X or Y lines are outputs (the manual doesn't say which, but
IIRC it's the Y lines). Only SHIFT, CTRL, and SHIFT LOCK are plain inputs,
and they only serve to modify the 7-bit code sent to the motherboard.

> If so, then there should be enough combinations of inputs on the keyboard
> port to allow the data signals to go through that, and then the GAME I/O
> has just enough inputs to cover all the status signals (HOPPER CHECK,
> MOTION CHECK, ERROR, BUSY, INDEX MARK, and READY).

I would just use the 6522. You need 12 data, plus 6 status listed above.
 Is there also a strobe of some sort (or is that READY?)? 8 lines on port
A, plus 4 on port B for the data, CA1 for the READY or strobe, and some
mixture of the remaining 4 data lines and the other three handshake lines
should do it. Don't bother with interrupts to start with. Leave the IER
all zeros, and just poll the IFR to look for the flag for CA1. Or just
poll it looking for a negative number (which means bit 7 is set, which
means one of the other flags is also set).

-- 
Pete						Peter Turnbull
						Network Manager
						University of York
Received on Mon Dec 30 2002 - 07:44:00 GMT

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