M200 interfacing

From: pete_at_dunnington.u-net.com <(pete_at_dunnington.u-net.com)>
Date: Mon Dec 30 13:09:25 2002

On Dec 30, 8:02, Sellam Ismail wrote:
> On Mon, 30 Dec 2002 pete_at_dunnington.u-net.com wrote:

> > That's an odd VIA. You mean a single 6522, right?

> Sorry, it was a typo. I meant two 8-bit ports.

Ah, I suspected it might be.

> This is starting to make sense.
> But alll the documenation I've read so far indicates that the function of
> the CA and CB lines is controlled by the PCR (Peripheral Control
> Register). I'll go poke a 0 into the IER and then see if I can get bits
> in the IFR to toggle by putting +5 on the CA1, CA2, CB1 or CB2 pins.

The easiest way to set it up to play with, is first to pull each of CA1,
CA2, CB1, and CB2 to +5V through four suitable resistors (anything from 1k
to 100k will do for this). Then write 0x00 into the PCR, which makes the
four handshake lines operate as independant inputs, with negative edge
triggering. Write 0x7F into the IER to disable all the interrupts (so the
Apple doesn't do any more resets), and 0x7F into the IFR to make sure it's
cleared. Then keep polling the IFR while you ground one or more of the
handshake pins. Look for any non-zero value. The relevant bits in the IFR
should become set, according to which line(s) you ground. Note that this
won't ever set bit 7 (MSB) of the IFR, because that only happens if
interrupts are enabled, unfortunately. Also remember you have to manually
clear the flags once they're set.

If you want to use positive-going edges instead of negative-going, use
pull-down resistors (don't rely on an unconnected input being low, it might
float to any value) and set 0x55 in the PCR.

If you are keen to use bit 7 in the IFR as a flag indicating "any input",
stick an RTI instruction on the end of your code, and store the address of
that RTI at IRQLOC ($03FE) first. That will prevent the interrupts
upsetting the Apple. Alternatively, have the Apple execute an SEI
instruction (0x78, sets the IRQ mask in the status register, to disable
interrupts). Then write 0x64 into the IER to disable all the interrupts
except from the handshake lines, and then write 0x9B into the IER to ensure
all the handshake interrupts really are enabled (the default state, after a
chip reset, is all disabled).

Pete						Peter Turnbull
						Network Manager
						University of York
Received on Mon Dec 30 2002 - 13:09:25 GMT

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