On Jan 22, 15:23, Richard Erlacher wrote:
> You wouldn't have any data on what, exactly, the voltages and timing for
the
> 1702A would be, would you?
This is from the Intel Data Catalog 1976:
t(ACH)
:<----- t(ACW) ------>: :<-->:
0V ___ :_____________________:__:_ :_______________________ _
ADDRESS \ / binary complement : : \ /: address of word \ /
X of address t.b.p. : : X : to be programmed X
-40 to 48V ___/ \_____________________:__:_/ \:_______________________/ \_
: : : :
: : : :
: : : t(VD)-->: :<--:
0V ___________________________: : : :
:___:______
pulsed V(DD) \ : : : / :
power supply :\ : : : /: :
-46 to -48V : \:____:______________:__/ : :
: : : : : :
: : : : : : :
: : -->: :<--- : : :
0V ___________________________: : : : t(ATW) :
:___:______
pulsed V(GG) \ : : : / :
power supply :\ : : : /: :
-35 to -40V \:________:__________:__/ :
: : : :
t(VW)--->: :<-- : :
: : -->: t(ATH)
:<---
0V _____________________________________ : :
______:_______
pulsed V(GG) \ :<-t(PW)-->: /
power supply \: :/
-35 to -40V \__________/
: : :
t(DW)---->: :<-- -->:
:<---t(DH)
: : : :
0V _______________________________ :___________________:
________
DATA data can \ /: :\ / data
can
change X : data stable : X
change
-46 to 48V _______________________________/ \:___________________:/
\__________
: :
min typ max
t(PW) Program Pulse Width 2ms 3ms V(GG)=-35V
V(DD)=V(PROG)=-48V
t(DW) Data Set-Up Time 25mms
t(DH) Data Hold Time 10mms
t(VW) V(DD), V(GG) Set-Up Time 100mms
t(VD) V(DD), V(GG) Hold Time 10mms 100mms
t(ACW) Addr.Compl. Set-Up Time 25mms
t(ACH) Addr.Compl. Hold Time 25mms
t(ATW) Addr.True Set-Up Time 10mms
t(ATH) Addr.True Hold Time 10mms
"mms" = microseconds. Input rise/fall times =< 1mms
Ambient temp 25C Vcc = 0V Vbb = +12V +/- 10% /CS = 0V
PROGRAMMING INFORMATION: 1702A and 1702AL family.
Initially all 2048 bits of the PROM are in the '0' state (outpiut low).
Information is introduced by selectively programming '1's (output high) in
the
proper bit locations.
All 8 address bits must be in the binary complement state when pulsed Vdd
and
Vgg move to their negative levels. The addresses must be held in their
binary
complement state for a minimum of 25 microsec after Vdd and Vgg have moved
to
their negative levels. The addresses must then make the transition to
their
true state a minimum of 10 microsec before the program pulse is applied.
The
addresses shouyld be programmed in the sequence 0 through 255 for a minimum
of
32 times. The eight output terminals are used as data inputs to determine
the
information pattern in the eight bits of each word. A low data level
(-48V)
will program a '1' and a high data input (0V) will program a '0'. All
eight
bits of one word are programmed simultaneously by setting the desired bit
information patterns on the data input terminals.
During the programming, Vgg, Vdd, and the Program Puilse are pulsed
signals.
See page 2 of the data sheet for required pin connections during
programming.
Pin Name Read Program
12 Vcc Vcc GND
13 Program Vcc Prog.Pulse
14 /CS GND GND
15 Vbb Vcc Vbb
16 Vgg Vgg Pulsed Vgg
22 Vcc Vcc GND
23 Vcc Vcc GND
24 Vdd Vdd Pulsed Vdd
--
Pete Peter Turnbull
Network Manager
University of York
Received on Tue Jan 22 2002 - 19:59:37 GMT