--- Mike <dogas_at_bellsouth.net> wrote:
> From: Ethan Dicks <erd_6502_at_yahoo.com>
>
> > >
> > > > The C3 was kinda cool... It was wild to see a box with multiple
> > > > CPUs...
> > That sounds wicked. I wonder how they handled the 12-bit bus of the
> > 6100.
>
> pins 19-22 on the standard OSI bus = A16 - A19 for extended addressing
> under the 6502 (multiuser and under software control of the PIA) and
> probably used natively under the 6100...
The 6100 has a 12-bit address bus (and presumably 3 bits of address
extension - EMA bits, as they are called on the PDP-8) *and* a 12-bit
data bus. _That's_ the one I was wondering about. For the address
stuff, externally, you can pretend that it has a 15-bit address bus,
and you won't have too many gyrations to perform. Where to stash the
extra 50% of data when you are sharing a box with a bunch of 8-bit
processors is the question.
I suppose you could design a buffer that performs two memory transactions,
one for D0-D7 and one for D8-D11, and write into a 64KB address space,
but personally, I'd rather design in the room for it. If the 6100
card had its own RAM, but you only permitted 8-bit I/O transfers, that
could resolve the problem, presuming you didn't have to have shared RAM
for the handoff scheme...
Dropping a 6100 onto a 16-bit bus could be easier, presuming there that
you didn't have to support 16-bit I/O. Again, limiting it to 8-bits
might be the easy way to go.
-ethan
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Received on Mon Jan 28 2002 - 12:44:45 GMT