Disk hardware emulation, was Re: Grandfather system RTE6/VM?

From: Peter C. Wallace <pcw_at_mesanet.com>
Date: Wed Dec 10 11:27:07 2003

On Wed, 10 Dec 2003, Patrick Finnegan wrote:

> On Wednesday 10 December 2003 11:27, Peter C. Wallace wrote:
> > On Wed, 10 Dec 2003, Patrick Finnegan wrote:
> > > "Knowing the encoding scheme" prevents this from being a
> > > "universal" interface. You'd need to make different version for,
> > > say, your PC/XT, your PDP-11 with an RQDXn, and TeleVideo TS816.
> > > (Or shouse I say "my" as those are all system I have that'd benefit
> > > from this). At most, (I think) you'd need a different cable set
> > > for all three of these if you didn't claim to "know" the encoding.
> >
> > No, thats not true, all you need to know is the encoding scheme...
> > The cabling is interface type specific.
>
> Not being an 'expert' in data encoding schemes for hard drives, I can't
> claim with 100% certainty... but I'm willing to bet there's systems out
> there that use things such as GCR (similar to the Apple ][ and
> Commodore floppy disk encoding schemes).
>
> Also, you'd have to take into account in your scheme that the data rate
> for different controllers may not match. For example, recording data
> on the 8" hard drive in the Televideo TS816 probably isn't the same
> 'data rate' as a common ST506 interface drive, even though the
> interfaces are similar.
>
> To me, it's pointless to create a design that's arbitrarily limited to
> just one encoding scheme if you don't have to. When you can simplify
> the design *and* make it more universal, why not?



I was not considering a design that would be limited to any particular drive
type, but rather that the logical "front end" of the emulator could be tweaked
for best performance by tailoring it to the specific drive. The actual
hardware to do the bitstream processing would most easily be done in a FPGA
so any changes would not require hardware modifications.


Heres what I envision:


A small (say 4x5") circuit card with a FPGA, a SDRAM SIMM socket (or
soldered-on SDRAM), an IDE drive interface, FPGA core power supply, and
perhaps built in level shifters and connectors for at least ST506, Q2000, and
SMD drives. A daughter board connector is provided for more exotic drive
hardware interfaces (RLxx HP79xx etc). The FPGA config could be downloaded
with a serial port or USB.

I guess Tony convinced me of the simplicty of the shift register track data
recording, but compression is still valuable for performance reasons - the
data can be easily compressed before storing in the IDE drive...




>
> Pat
> --
> Purdue University ITAP/RCS
> Information Technology at Purdue
> Research Computing and Storage
> http://www.itap.purdue.edu/rcs/
>

Peter Wallace
Mesa Electronics
Received on Wed Dec 10 2003 - 11:27:07 GMT

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