Sellam Ismail,
I'm either being imprecise or various readings I have done were
imprecise. The reference to "one cycle" instruction may have been referring
to there being 2 cpu cycles per clock cycle. Also, there's the "pipelining"
some say the 6502 does when the last (or only) byte of an instruction is
acted upon simultaneous to next instruction's 1st byte (opcode) being
fetched
So perhaps "one instruction per clock cycle" may be awfully close with
pipelining and with use of zero page.
Of course, we're talking Apple ]['s which, if I can trust my memory,
steal every other clock cycle to refresh memory.
Cheers, - Jim
Jim Keohane, Multi-Platforms, Inc.
"It's not whether you win or lose. It's whether you win!"
----- Original Message -----
From: "Sellam Ismail" <foo_at_siconic.com>
To: <cctalk_at_classiccmp.org>
Sent: Friday, February 07, 2003 18:40
Subject: Re: Assembly on a Apple IIc+
> On Fri, 7 Feb 2003, Jim Keohane wrote:
>
> > p.s. I also did quite well with 6502 asm code in cpu speed tests vs
> > 80x86 and Z80 programmers. The zero page, for all intents and purposes,
> > is 256 registers. 6502 is single cycle instruction execution. Look up
> > definitions of RISC and the 6502 is arguably RISC-like.
>
> No 6502 instruction takes less than 2 cycles to complete.
>
> Sellam Ismail Vintage Computer
Festival
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Received on Sat Feb 08 2003 - 10:20:01 GMT