Assembly on a Apple IIc+

From: <(>
Date: Sat Feb 8 18:27:01 2003

On Feb 8, 16:12, Jim Keohane wrote:

> I'll type more slowly:
> Question #1:
> If an instruction that takes two cpu cycles (as Sellam Ismail
cited as a
> minimum) and there are 2 cpu cycles per clock cycle then how many
> cycles did this one instruction take?
> Answer: one.

NO. There NOT two CPU cycles per clock cycle. Sellam cited two CLOCK
cycles minimum per instruction. He is correct. I've been been
building 6502-based devices and programming 6502 code on and off since
1981, and I suspect Sellam has been arund 6502s nearly as long; we're
both accustomed to calculating how many cycles routines take. The 6502
uses several clock cycles per CPU cycle -- if by cycle you mean a
fetch-execute cycle. That's exactly the opposite of what you're

> OK. OK. I'm being cute. But the 6502, sans Woz's Apple ][
> sneakiness for video, can do two memory fetches per clock cycle.

No, it can't. Go read the data sheet. The *system* can, providing
your memory is fast enough that you can run it twice as fast as the CPU
-- which the Apple and some other machines did -- and providing you
have *something else* (eg, the video) doing its memory access only
during the clock phase that the 6502 doesn't use for memory access. It
is the clock edges that trigger the 6502 to perform the memory access.

> Question #2:
> If someone writes "pipelining" and encloses it within quotes does
> indicate to you that the term is being used, well, advisably?
> Answer: Visit and search for "pipelining" and
6502 (or
> related processor).


> =====excerpt 3=======================
> The 6502 _IS_ pipelined, but in ways that are not very dramatic or
> obvious
> unless you look at the CPU's internal operation in detail. Rockwell
> the
> pipelining in their 6502 user's guide years ago, it is essentially
> When you do a ADC of something, the last cycle of the instruction is
> the
> actual data byte is read in, right? Immediately after that the next
> is
> read so the next instruction has started, right? So when did the 6502
> It added while the next opcode was being read. The accumulator does
> actually hold the new value until sometime during the second half
> exactly where) of the opcode cycle of the next instruction.
> That's pipelining. It saves you a cycle on every instruction that
does an
> operation. It may not be as spectacular as what's being done on the
> RISCs these days but it is essentially pipelining.

Yes, but only on a small number of the instructions. I'm sure other
microprocessors of the day did that, Rockwell marketing not

> I'd say you got me on the "one cycle per instruction" but you
jumped the
> gun on the pipelining issue. OK?

Well, maybe, but the 6502 is not basically a pipelined processor, in
the sense that only a few instructions do anything close to pipelining,
and not even all the intructions that use the ALU do so.

Pete						Peter Turnbull
						Network Manager
						University of York
Received on Sat Feb 08 2003 - 18:27:01 GMT

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