Wanted : Pinouts for 9311, 93L14, 8273 chips

From: Marvin Johnston <marvin_at_rain.org>
Date: Sat Jan 18 18:51:00 2003

Tony Duell wrote:
>
> I'm fixing some old HP computer hardware (a 9830 computer and its 9866
> thermal printer), and I've come up against a few ICs I don't have pinouts
> for :-(.
>
> If anyone has them, could they fill in the tables below :
>
> Fairchild 9311 (4 bit -> 16 line decoder?)

One-Of-Sixteen Decoder/Demultiplexer

The 9311 is a TTL/MSI Multi-Purpose Decoder designed to accept four
inputs and provide 16 mutually exclusive outputs. The Circuit uses TTL
for high speed and high fan-out capability, and is compatible with all
members of the Fairchild TTL family.

A0 - A3 - Address Inputs
E0, E1 - AND enable (Active LOW) inputs
0 - 15 (Active LOW) Outputs, 10 U.L. is the output LOW drive factor, and
20 U.L. is the output HIGH drive factor.

> 1 : 0
> 2 : 1
> 3 : 2
> 4 : 3
> 5 : 4
> 6 : 5
> 7 : 6
> 8 : 7
> 9 : 8
> 10 : 9
> 11 : 10
> 12 : Gnd
> 13 : 11
> 14 : 12
> 15 : 13
> 16 : 14
> 17 : 15
> 18 : E0
> 19 : E1
> 20 : A0
> 21 : A1
> 22 : A2
> 23 : A3
> 24 : Vcc
>
> Fairchild 93L14 (latch?)
>

Low Power Quad Latch - LPTTL/MSI is a multifunctional 4-bit latch. The
latch is desgined for general purpose storage applications in high speed
digital systems. All inputs feature diode clamping to reduce negative
line transients. All outputs have active pull-up circuitry to provide
low impedance in both logit states for good ac noise immunity.

E - Enable (Active LOW) Input
D0 - D3 Data Inputs
S0 - S3 Set (Active LOW) Inputs
MR - Master Reset (Active LOW) Input
Q0 - Q3 Latch Outputs

> 1 : E
> 2 : S0
> 3 : D0
> 4 : D1
> 5 : S2
> 6 : D2
> 7 : S3
> 8 : Gnd
> 9 : MR
> 10 : Q3
> 11 : S3
> 12 : Q2
> 13 : Q1
> 14 : S1
> 15 : Q0
> 16 : Vcc
>
> Signetics 8273 (10 bit serial-in, parallel out shift register)

The 8273 10-bit Shift Register is an array of binary elements
interconnected to perform the serial-in, parallel-out shift function.
This device utilizes a common buffered reset and operates from either a
positive or negative edge clock pulse. Clock 1 is triggered by a
negative going clock pulse and clock 2 is triggered by a positive going
clock pulse. The circuit configuration is arranged as a single serial
input register with ten true parallel outputs.

>
> 1 : Q6
> 2 : Q7
> 3 : Q8
> 4 : Q9
> 5 : Q10
> 6 : Clock 1
> 7 : Clock 2
> 8 : Gnd
> 9 : Reset
> 10 : Serial In
> 11 : Q1
> 12 : Q2
> 13 : Q3
> 14 : Q4
> 15 : Q5
> 16 : Vcc

Truth Table

Input Reset (active low) Clock 1 Clock 2 On+1
  1 1 Pulse 0 1
  0 1 Pulse 0 0
  1 1 1 Pulse 1
  0 1 1 Pulse 0
  1 1 Pulse 1 Q
  0 1 Pulse 1 Q
  1 1 0 Pulse Q
  0 1 0 Pulse Q

Note: The unused clock input performs the INHIBIT function.
Reset = 0 > Q = 0




>
> Thanks in advance for any help
>
> -tony
Received on Sat Jan 18 2003 - 18:51:00 GMT