>From: "ben franchuk" <bfranchuk_at_jetnet.ab.ca>
>
>Dwight K. Elvey wrote:
>
>>
>> Hi
>> All make the assumption that you must make 8 bit/16bit
>> or, in your case, 20 bit. One can make a 1 bit alu that
>> can have data width controlled by instruction. It may
>> not be fast at math but much processor time is consumed
>> just looking at true/false. If your model doesn't require
>> passing data through the alu for mem/mem and mem/io moves,
>> a single bitter makes sense.
>> ( My Nicolet is a 20 bit machine. )
>
>Darn! All the good computer names are taken. :)
>Do you have any more information?
>
>> Dwight
>
>Some day I would like to see a DECIMAL computer in
>TLL or FPGA like the early decimal machines.
>Ben.
Hi Ben
I didn't build it, I just made it work. A real pain,
since I didn't have any schematics and it had several
problems. There are a couple of pictures at:
http://www.rdrop.com/~jimw/jcgm-vcfiv.shtml
Look down 8 rows. The first 2 pictures in that row
are my Nicolet machine ( It has 12Kx20 core ). It is
all ttl/dtl, thought. Notice the front panel switch
position. It is 7600 octal, the boot vector in core.
One of the interesting things is the ALU. It has a
5 input port adder. One can select from, ALU, ALU*, MEM,
MEM* and "one" to add together. One can do a lot with
this combination.
Anyway, back on the original subject, there are also
some interesting minimal instruction processors described
out there. As I recall, there was one that had only 4
operations. SUBtract was one of them ( considered more
important than an ADD ).
I've been toying with making a single bit relay based
computer. My intent is to make the main memory bank using
reed relays with a magnet to bias them. The idea is that
the external magnet has just enough effect that if the
reed relay is closed, it stays that way. If it is opened
it stays open. One would arrange these relays in an array
with small ceramic magnets, north and south poles alternating
so that there is no cumulative bias. Writing to the reeds,
coil in opposite directions causes it to open or close.
Data is handled by a shift register so that the bus is
always 1 bit wide. It'll be slow but what the heck.
To make things a little more complicated, I expect to use
3 phase clocking. With this, I can use overlapped clocks,
without racing.
Dwight
Received on Thu May 22 2003 - 20:55:01 BST